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STM32L4 USB: move HAL_PCD_EP_Abort function
This function is for USB_OTG_FS devices only. Move it in the correct place (in "#ifdef USB_OTG_FS" area).
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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c

Lines changed: 80 additions & 80 deletions
Original file line numberDiff line numberDiff line change
@@ -741,6 +741,86 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
741741
}
742742
}
743743

744+
// MBED PATCH
745+
/**
746+
* @brief Abort a transaction.
747+
* @param hpcd: PCD handle
748+
* @param ep_addr: endpoint address
749+
* @retval HAL status
750+
*/
751+
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
752+
{
753+
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
754+
HAL_StatusTypeDef ret = HAL_OK;
755+
USB_OTG_EPTypeDef *ep;
756+
757+
if ((0x80 & ep_addr) == 0x80)
758+
{
759+
ep = &hpcd->IN_ep[ep_addr & 0x7F];
760+
}
761+
else
762+
{
763+
ep = &hpcd->OUT_ep[ep_addr];
764+
}
765+
766+
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
767+
768+
ep->num = ep_addr & 0x7F;
769+
ep->is_in = ((ep_addr & 0x80) == 0x80);
770+
771+
USB_EPSetNak(hpcd->Instance, ep);
772+
773+
if ((0x80 & ep_addr) == 0x80)
774+
{
775+
ret = USB_EPStopXfer(hpcd->Instance , ep);
776+
if (ret == HAL_OK)
777+
{
778+
ret = USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
779+
}
780+
}
781+
else
782+
{
783+
/* Set global NAK */
784+
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
785+
786+
/* Read all entries from the fifo so global NAK takes effect */
787+
while (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
788+
{
789+
PCD_ReadRxFifo(hpcd);
790+
}
791+
792+
/* Stop the transfer */
793+
ret = USB_EPStopXfer(hpcd->Instance , ep);
794+
if (ret == HAL_BUSY)
795+
{
796+
/* If USB_EPStopXfer returns HAL_BUSY then a setup packet
797+
* arrived after the rx fifo was processed but before USB_EPStopXfer
798+
* was called. Process the rx fifo one more time to read the
799+
* setup packet.
800+
*
801+
* Note - after the setup packet has been received no further
802+
* packets will be received over USB. This is because the next
803+
* phase (data or status) of the control transfer started by
804+
* the setup packet will be naked until global nak is cleared.
805+
*/
806+
while (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
807+
{
808+
PCD_ReadRxFifo(hpcd);
809+
}
810+
811+
ret = USB_EPStopXfer(hpcd->Instance , ep);
812+
}
813+
814+
/* Clear global nak */
815+
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
816+
}
817+
818+
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
819+
820+
return ret;
821+
}
822+
// MBED PATCH
823+
744824
#endif /* USB_OTG_FS */
745825

746826
#if defined (USB)
@@ -1246,86 +1326,6 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
12461326
return HAL_OK;
12471327
}
12481328

1249-
// MBED PATCH
1250-
/**
1251-
* @brief Abort a transaction.
1252-
* @param hpcd: PCD handle
1253-
* @param ep_addr: endpoint address
1254-
* @retval HAL status
1255-
*/
1256-
HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
1257-
{
1258-
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
1259-
HAL_StatusTypeDef ret = HAL_OK;
1260-
USB_OTG_EPTypeDef *ep;
1261-
1262-
if ((0x80 & ep_addr) == 0x80)
1263-
{
1264-
ep = &hpcd->IN_ep[ep_addr & 0x7F];
1265-
}
1266-
else
1267-
{
1268-
ep = &hpcd->OUT_ep[ep_addr];
1269-
}
1270-
1271-
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
1272-
1273-
ep->num = ep_addr & 0x7F;
1274-
ep->is_in = ((ep_addr & 0x80) == 0x80);
1275-
1276-
USB_EPSetNak(hpcd->Instance, ep);
1277-
1278-
if ((0x80 & ep_addr) == 0x80)
1279-
{
1280-
ret = USB_EPStopXfer(hpcd->Instance , ep);
1281-
if (ret == HAL_OK)
1282-
{
1283-
ret = USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
1284-
}
1285-
}
1286-
else
1287-
{
1288-
/* Set global NAK */
1289-
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK;
1290-
1291-
/* Read all entries from the fifo so global NAK takes effect */
1292-
while (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
1293-
{
1294-
PCD_ReadRxFifo(hpcd);
1295-
}
1296-
1297-
/* Stop the transfer */
1298-
ret = USB_EPStopXfer(hpcd->Instance , ep);
1299-
if (ret == HAL_BUSY)
1300-
{
1301-
/* If USB_EPStopXfer returns HAL_BUSY then a setup packet
1302-
* arrived after the rx fifo was processed but before USB_EPStopXfer
1303-
* was called. Process the rx fifo one more time to read the
1304-
* setup packet.
1305-
*
1306-
* Note - after the setup packet has been received no further
1307-
* packets will be received over USB. This is because the next
1308-
* phase (data or status) of the control transfer started by
1309-
* the setup packet will be naked until global nak is cleared.
1310-
*/
1311-
while (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
1312-
{
1313-
PCD_ReadRxFifo(hpcd);
1314-
}
1315-
1316-
ret = USB_EPStopXfer(hpcd->Instance , ep);
1317-
}
1318-
1319-
/* Clear global nak */
1320-
USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK;
1321-
}
1322-
1323-
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
1324-
1325-
return ret;
1326-
}
1327-
// MBED PATCH
1328-
13291329
/**
13301330
* @brief Set a STALL condition over an endpoint.
13311331
* @param hpcd: PCD handle

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