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| 1 | +/* |
| 2 | + * Copyright (c) 2013 Nordic Semiconductor ASA |
| 3 | + * All rights reserved. |
| 4 | + * |
| 5 | + * Redistribution and use in source and binary forms, with or without modification, |
| 6 | + * are permitted provided that the following conditions are met: |
| 7 | + * |
| 8 | + * 1. Redistributions of source code must retain the above copyright notice, this list |
| 9 | + * of conditions and the following disclaimer. |
| 10 | + * |
| 11 | + * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA |
| 12 | + * integrated circuit in a product or a software update for such product, must reproduce |
| 13 | + * the above copyright notice, this list of conditions and the following disclaimer in |
| 14 | + * the documentation and/or other materials provided with the distribution. |
| 15 | + * |
| 16 | + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be |
| 17 | + * used to endorse or promote products derived from this software without specific prior |
| 18 | + * written permission. |
| 19 | + * |
| 20 | + * 4. This software, with or without modification, must only be used with a |
| 21 | + * Nordic Semiconductor ASA integrated circuit. |
| 22 | + * |
| 23 | + * 5. Any software provided in binary or object form under this license must not be reverse |
| 24 | + * engineered, decompiled, modified and/or disassembled. |
| 25 | + * |
| 26 | + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 27 | + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 28 | + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 29 | + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| 30 | + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 31 | + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 32 | + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| 33 | + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 34 | + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 35 | + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 36 | + * |
| 37 | + */ |
| 38 | + |
| 39 | +#include "us_ticker_api.h" |
| 40 | +#include "common_rtc.h" |
| 41 | +#include "app_util.h" |
| 42 | +#include "nrf_drv_common.h" |
| 43 | +#include "lp_ticker_api.h" |
| 44 | +#include "mbed_critical.h" |
| 45 | + |
| 46 | +#if defined(NRF52_ERRATA_20) |
| 47 | + #include "softdevice_handler.h" |
| 48 | +#endif |
| 49 | + |
| 50 | +//------------------------------------------------------------------------------ |
| 51 | +// Common stuff used also by lp_ticker and rtc_api (see "common_rtc.h"). |
| 52 | +// |
| 53 | +#include "app_util_platform.h" |
| 54 | + |
| 55 | +bool m_common_rtc_enabled = false; |
| 56 | +uint32_t volatile m_common_rtc_overflows = 0; |
| 57 | + |
| 58 | +__STATIC_INLINE void rtc_ovf_event_check(void) |
| 59 | +{ |
| 60 | + if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) { |
| 61 | + nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW); |
| 62 | + // Don't disable this event. It shall occur periodically. |
| 63 | + |
| 64 | + ++m_common_rtc_overflows; |
| 65 | + } |
| 66 | +} |
| 67 | + |
| 68 | +#if defined(TARGET_MCU_NRF51822) |
| 69 | +void common_rtc_irq_handler(void) |
| 70 | +#else |
| 71 | +void COMMON_RTC_IRQ_HANDLER(void) |
| 72 | +#endif |
| 73 | +{ |
| 74 | + rtc_ovf_event_check(); |
| 75 | + |
| 76 | +#if DEVICE_LOWPOWERTIMER |
| 77 | + if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT)) { |
| 78 | + |
| 79 | + lp_ticker_irq_handler(); |
| 80 | + } |
| 81 | +#endif |
| 82 | +} |
| 83 | + |
| 84 | +// Function for fix errata 20: RTC Register values are invalid |
| 85 | +__STATIC_INLINE void errata_20(void) |
| 86 | +{ |
| 87 | +#if defined(NRF52_ERRATA_20) |
| 88 | + if (!softdevice_handler_is_enabled()) |
| 89 | + { |
| 90 | + NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; |
| 91 | + NRF_CLOCK->TASKS_LFCLKSTART = 1; |
| 92 | + |
| 93 | + while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) |
| 94 | + { |
| 95 | + } |
| 96 | + } |
| 97 | + NRF_RTC1->TASKS_STOP = 0; |
| 98 | +#endif |
| 99 | +} |
| 100 | + |
| 101 | +void RTC1_IRQHandler(void); |
| 102 | + |
| 103 | +void common_rtc_init(void) |
| 104 | +{ |
| 105 | + if (m_common_rtc_enabled) { |
| 106 | + return; |
| 107 | + } |
| 108 | + |
| 109 | + errata_20(); |
| 110 | + |
| 111 | + NVIC_SetVector(RTC1_IRQn, (uint32_t)RTC1_IRQHandler); |
| 112 | + |
| 113 | + // RTC is driven by the low frequency (32.768 kHz) clock, a proper request |
| 114 | + // must be made to have it running. |
| 115 | + // Currently this clock is started in 'SystemInit' (see "system_nrf51.c" |
| 116 | + // or "system_nrf52.c", respectively). |
| 117 | + |
| 118 | + nrf_rtc_prescaler_set(COMMON_RTC_INSTANCE, 0); |
| 119 | + |
| 120 | +#if defined(TARGET_MCU_NRF51822) |
| 121 | + nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT); |
| 122 | +#endif |
| 123 | +#if DEVICE_LOWPOWERTIMER |
| 124 | + nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT); |
| 125 | +#endif |
| 126 | + nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW); |
| 127 | + |
| 128 | + // Interrupts on all related events are enabled permanently. Particular |
| 129 | + // events will be enabled or disabled as needed (such approach is more |
| 130 | + // energy efficient). |
| 131 | + nrf_rtc_int_enable(COMMON_RTC_INSTANCE, |
| 132 | +#if DEVICE_LOWPOWERTIMER |
| 133 | + LP_TICKER_INT_MASK | |
| 134 | +#endif |
| 135 | + NRF_RTC_INT_OVERFLOW_MASK); |
| 136 | + |
| 137 | + // This event is enabled permanently, since overflow indications are needed |
| 138 | + // continuously. |
| 139 | + nrf_rtc_event_enable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK); |
| 140 | + // All other relevant events are initially disabled. |
| 141 | + nrf_rtc_event_disable(COMMON_RTC_INSTANCE, 0 | |
| 142 | +#if defined(TARGET_MCU_NRF51822) |
| 143 | + OS_TICK_INT_MASK | |
| 144 | +#endif |
| 145 | +#if DEVICE_LOWPOWERTIMER |
| 146 | + LP_TICKER_INT_MASK |
| 147 | +#endif |
| 148 | + ); |
| 149 | + |
| 150 | + nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE), |
| 151 | +#ifdef NRF51 |
| 152 | + APP_IRQ_PRIORITY_LOW |
| 153 | +#elif defined(NRF52) || defined(NRF52840_XXAA) |
| 154 | + APP_IRQ_PRIORITY_LOWEST |
| 155 | +#endif |
| 156 | + ); |
| 157 | + |
| 158 | + nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START); |
| 159 | + |
| 160 | + m_common_rtc_enabled = true; |
| 161 | +} |
| 162 | + |
| 163 | +__STATIC_INLINE void rtc_ovf_event_safe_check(void) |
| 164 | +{ |
| 165 | + core_util_critical_section_enter(); |
| 166 | + |
| 167 | + rtc_ovf_event_check(); |
| 168 | + |
| 169 | + core_util_critical_section_exit(); |
| 170 | +} |
| 171 | + |
| 172 | + |
| 173 | +uint32_t common_rtc_32bit_ticks_get(void) |
| 174 | +{ |
| 175 | + uint32_t ticks; |
| 176 | + uint32_t prev_overflows; |
| 177 | + |
| 178 | + do { |
| 179 | + prev_overflows = m_common_rtc_overflows; |
| 180 | + |
| 181 | + ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); |
| 182 | + // The counter used for time measurements is less than 32 bit wide, |
| 183 | + // so its value is complemented with the number of registered overflows |
| 184 | + // of the counter. |
| 185 | + ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS); |
| 186 | + |
| 187 | + // Check in case that OVF occurred during execution of a RTC handler (apply if call was from RTC handler) |
| 188 | + // m_common_rtc_overflows might been updated in this call. |
| 189 | + rtc_ovf_event_safe_check(); |
| 190 | + |
| 191 | + // If call was made from a low priority level m_common_rtc_overflows might have been updated in RTC handler. |
| 192 | + } while (m_common_rtc_overflows != prev_overflows); |
| 193 | + |
| 194 | + return ticks; |
| 195 | +} |
| 196 | + |
| 197 | +uint64_t common_rtc_64bit_us_get(void) |
| 198 | +{ |
| 199 | + uint32_t ticks = common_rtc_32bit_ticks_get(); |
| 200 | + // [ticks -> microseconds] |
| 201 | + return ROUNDED_DIV(((uint64_t)ticks) * 1000000, RTC_INPUT_FREQ); |
| 202 | +} |
| 203 | + |
| 204 | +void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel, |
| 205 | + uint32_t int_mask) |
| 206 | +{ |
| 207 | + // The internal counter is clocked with a frequency that cannot be easily |
| 208 | + // multiplied to 1 MHz, therefore besides the translation of values |
| 209 | + // (microsecond <-> ticks) a special care of overflows handling must be |
| 210 | + // taken. Here the 32-bit timestamp value is complemented with information |
| 211 | + // about current the system up time of (ticks + number of overflows of tick |
| 212 | + // counter on upper bits, converted to microseconds), and such 64-bit value |
| 213 | + // is then translated to counter ticks. Finally, the lower 24 bits of thus |
| 214 | + // calculated value is written to the counter compare register to prepare |
| 215 | + // the interrupt generation. |
| 216 | + uint64_t current_time64 = common_rtc_64bit_us_get(); |
| 217 | + // [add upper 32 bits from the current time to the timestamp value] |
| 218 | + uint64_t timestamp64 = us_timestamp + |
| 219 | + (current_time64 & ~(uint64_t)0xFFFFFFFF); |
| 220 | + // [if the original timestamp value happens to be after the 32 bit counter |
| 221 | + // of microsends overflows, correct the upper 32 bits accordingly] |
| 222 | + if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF)) { |
| 223 | + timestamp64 += ((uint64_t)1 << 32); |
| 224 | + } |
| 225 | + // [microseconds -> ticks, always round the result up to avoid too early |
| 226 | + // interrupt generation] |
| 227 | + uint32_t compare_value = |
| 228 | + (uint32_t)CEIL_DIV((timestamp64) * RTC_INPUT_FREQ, 1000000); |
| 229 | + |
| 230 | + |
| 231 | + core_util_critical_section_enter(); |
| 232 | + // The COMPARE event occurs when the value in compare register is N and |
| 233 | + // the counter value changes from N-1 to N. Therefore, the minimal safe |
| 234 | + // difference between the compare value to be set and the current counter |
| 235 | + // value is 2 ticks. This guarantees that the compare trigger is properly |
| 236 | + // setup before the compare condition occurs. |
| 237 | + uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2; |
| 238 | + if ((int)(compare_value - closest_safe_compare) <= 0) { |
| 239 | + compare_value = closest_safe_compare; |
| 240 | + } |
| 241 | + |
| 242 | + nrf_rtc_cc_set(COMMON_RTC_INSTANCE, cc_channel, RTC_WRAP(compare_value)); |
| 243 | + nrf_rtc_event_enable(COMMON_RTC_INSTANCE, int_mask); |
| 244 | + |
| 245 | + core_util_critical_section_exit(); |
| 246 | +} |
| 247 | + |
| 248 | +// Since there is no SysTick on NRF51, the RTC1 channel 1 is used as an |
| 249 | +// alternative source of RTOS ticks. |
| 250 | +#if defined(TARGET_MCU_NRF51822) |
| 251 | + |
| 252 | +#include "mbed_toolchain.h" |
| 253 | + |
| 254 | + |
| 255 | +#define MAX_RTC_COUNTER_VAL ((1uL << RTC_COUNTER_BITS) - 1) |
| 256 | + |
| 257 | +#ifndef RTC1_CONFIG_FREQUENCY |
| 258 | + #define RTC1_CONFIG_FREQUENCY 32678 // [Hz] |
| 259 | +#endif |
| 260 | + |
| 261 | + |
| 262 | + |
| 263 | +void COMMON_RTC_IRQ_HANDLER(void) |
| 264 | +{ |
| 265 | + if(!nrf_rtc_event_pending(COMMON_RTC_INSTANCE, OS_TICK_EVENT)) { |
| 266 | + common_rtc_irq_handler(); |
| 267 | + } |
| 268 | +} |
| 269 | + |
| 270 | +IRQn_Type mbed_get_m0_tick_irqn() |
| 271 | +{ |
| 272 | + return SWI3_IRQn; |
| 273 | +} |
| 274 | + |
| 275 | + |
| 276 | +#endif // defined(TARGET_MCU_NRF51822) |
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