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rogeryourogeryou
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Add OSPI driver
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‎TESTS/mbed_hal/ospi/flash_configs/MX25LM51245G_config.h

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/* mbed Microcontroller Library
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* Copyright (c) 2018-2020 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_OSPI_FLASH_MX25LM51245G_H
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#define MBED_OSPI_FLASH_MX25LM51245G_H
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#define OSPI_FLASH_CHIP_STRING "macronix MX25LM51245G"
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#define OSPI_CMD_RDID 0x9F
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// Command for reading status register
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#define OSPI_CMD_RDSR 0x05
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// Command for reading configuration register
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#define OSPI_CMD_RDCR0 0x15
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#define OSPI_CMD_RDCR2 0x71
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// Command for writing status/configuration register
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#define OSPI_CMD_WRSR 0x01
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#define OSPI_CMD_WRCR2 0x72
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// Command for reading security register
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#define OSPI_CMD_RDSCUR 0x2B
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// Command for setting Reset Enable
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#define OSPI_CMD_RSTEN 0x66
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// Command for setting Reset
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#define OSPI_CMD_RST 0x99
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// Command for setting write enable
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#define OSPI_CMD_WREN 0x06
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// Command for setting write disable
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#define OSPI_CMD_WRDI 0x04
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// WRSR operations max time [us] (datasheet max time + 15%)
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#define OSPI_WRSR_MAX_TIME 34500 // 30ms
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// general wait max time [us]
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#define OSPI_WAIT_MAX_TIME 100000 // 100ms
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// Commands for writing (page programming)
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// Only single/octal mode supported with this memory
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// So only single 1-1-1 mode in this OSPI config
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//#define OSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
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#define OSPI_CMD_WRITE_1IO 0x12 // 4 byte addr 1-1-1 mode
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#define OSPI_CMD_WRITE_OPI 0x12 // 8-8-8 mode
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// write operations max time [us] (datasheet max time + 15%)
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#define OSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
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#define OSPI_PAGE_SIZE 256 // 256B
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#define OSPI_SECTOR_SIZE 4096 // 4kB
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#define OSPI_SECTOR_COUNT 2048
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// Commands for reading
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// Only single/octal mode supported with this memory
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// So only single 1-1-1 mode in this OSPI config
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#define OSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
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//#define OSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
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#define OSPI_CMD_READ_1IO 0x13 // 4 byte addr 1-1-1 mode
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#define OSPI_CMD_READ_OPI 0xEC // 8-8-8 mode
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#define OSPI_CMD_READ_DOPI 0xEE // 8D-8D-8D mode
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#define OSPI_READ_1IO_DUMMY_CYCLE 0
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#define OSPI_READ_FAST_DUMMY_CYCLE 8
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#define OSPI_READ_8IO_DUMMY_CYCLE 20
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// Commands for erasing
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#define OSPI_CMD_ERASE_SECTOR 0x21 // 4kB
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#define OSPI_CMD_ERASE_SECTOR_4B 0x21 // 4kB
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//#define OSPI_CMD_ERASE_BLOCK_32 // not supported, only ersae block 64
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#define OSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
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#define OSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
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// erase operations max time [us] (datasheet max time + 15%)
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#define OSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms
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#define OSPI_ERASE_BLOCK_64_MAX_TIME 2400000 // 2s
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// max frequency for basic rw operation (for fast mode)
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#define OSPI_COMMON_MAX_FREQUENCY 66000000
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#define OSPI_STATUS_REG_SIZE 2 //2 ??
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#define OSPI_CONFIG_REG_0_SIZE 1
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#define OSPI_CONFIG_REG_1_SIZE 2
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#define OSPI_CONFIG_REG_2_SIZE 2 //1 byte in spi and sopi mode;2 byte in dopi
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#define OSPI_SECURITY_REG_SIZE 1
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#define OSPI_MAX_REG_SIZE 2
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// status register
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#define STATUS_BIT_WIP (1 << 0) // write in progress bit
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#define STATUS_BIT_WEL (1 << 1) // write enable latch
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#define STATUS_BIT_BP0 (1 << 2) //
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#define STATUS_BIT_BP1 (1 << 3) //
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#define STATUS_BIT_BP2 (1 << 4) //
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#define STATUS_BIT_BP3 (1 << 5) //
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//#define STATUS_BIT_QE (1 << 6) // Not supported
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//#define STATUS_BIT_SRWD (1 << 7) // Not supported
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// configuration register 0
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// bit 0, 1, 2, 4, 5, 7 reserved
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#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
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#define CONFIG2_OPI_EN_ADDR 0x00000000
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// configuration register 2
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#define CONFIG2_BIT_SOPI_EN (1 << 0) // sopi mode enable
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#define CONFIG2_BIT_DOPI_EN (1 << 1) // dopi mode enable
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#define CONFIG2_SPI_EN 0 // spi mode enable
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#define OCTA_ENABLE() \
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\
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uint8_t reg_data[OSPI_CONFIG_REG_2_SIZE]; \
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\
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memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
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if (write_enable(ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = CONFIG2_BIT_SOPI_EN; \
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ospi.cmd.configure(MODE_1_1_1, ADDR_SIZE_32, ALT_SIZE_8); \
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if (write_config_register_2(OSPI_CMD_WRCR2, CONFIG2_OPI_EN_ADDR, \
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reg_data, 1, ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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ospi.cmd.configure(MODE_8_8_8, ADDR_SIZE_32, ALT_SIZE_8); \
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WAIT_FOR(WRSR_MAX_TIME, ospi); \
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memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
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\
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if (read_config_register_2(OSPI_CMD_RDCR2, CONFIG2_OPI_EN_ADDR, \
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reg_data, OSPI_CONFIG_REG_2_SIZE, ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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return (reg_data[0] == CONFIG2_BIT_SOPI_EN ? \
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OSPI_STATUS_OK : OSPI_STATUS_ERROR)
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#define OCTA_DISABLE() \
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\
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uint8_t reg_data[OSPI_CONFIG_REG_2_SIZE]; \
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\
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memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
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if (write_enable(ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = CONFIG2_SPI_EN; \
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if (write_config_register_2(OSPI_CMD_WRCR2, CONFIG2_OPI_EN_ADDR, \
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reg_data, 1, ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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ospi.cmd.configure(MODE_1_1_1, ADDR_SIZE_32, ALT_SIZE_8); \
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WAIT_FOR(WRSR_MAX_TIME, ospi); \
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memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
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if (read_config_register_2(OSPI_CMD_RDCR2, CONFIG2_OPI_EN_ADDR, \
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reg_data, 1, ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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return (reg_data[0] == CONFIG2_SPI_EN ? \
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OSPI_STATUS_OK : OSPI_STATUS_ERROR)
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#define OCTA_DTR_ENABLE() \
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\
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uint8_t reg_data[OSPI_CONFIG_REG_2_SIZE]; \
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\
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memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
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if (write_enable(ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = CONFIG2_BIT_DOPI_EN; \
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ospi.cmd.configure(MODE_1_1_1, ADDR_SIZE_32, ALT_SIZE_8); \
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if (write_config_register_2(OSPI_CMD_WRCR2, CONFIG2_OPI_EN_ADDR, \
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reg_data, 1, ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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ospi.cmd.configure(MODE_8D_8D_8D, ADDR_SIZE_32, ALT_SIZE_8); \
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WAIT_FOR(WRSR_MAX_TIME, ospi); \
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memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
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if (read_config_register_2(OSPI_CMD_RDCR2, CONFIG2_OPI_EN_ADDR, \
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reg_data, OSPI_CONFIG_REG_2_SIZE, ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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return (reg_data[0] == CONFIG2_BIT_DOPI_EN ? \
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OSPI_STATUS_OK : OSPI_STATUS_ERROR)
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#define OCTA_DTR_DISABLE() \
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\
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uint8_t reg_data[OSPI_CONFIG_REG_2_SIZE]; \
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\
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memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
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if (write_enable(ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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\
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reg_data[0] = CONFIG2_SPI_EN; \
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if (write_config_register_2(OSPI_CMD_WRCR2, CONFIG2_OPI_EN_ADDR, \
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reg_data, OSPI_CONFIG_REG_2_SIZE, ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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ospi.cmd.configure(MODE_1_1_1, ADDR_SIZE_32, ALT_SIZE_8); \
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WAIT_FOR(WRSR_MAX_TIME, ospi); \
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memset(reg_data, 0, OSPI_CONFIG_REG_2_SIZE); \
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if (read_config_register_2(OSPI_CMD_RDCR2, CONFIG2_OPI_EN_ADDR, \
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reg_data, OSPI_CONFIG_REG_2_SIZE, ospi) != OSPI_STATUS_OK) { \
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return OSPI_STATUS_ERROR; \
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} \
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return (reg_data[0] == CONFIG2_SPI_EN ? \
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OSPI_STATUS_OK : OSPI_STATUS_ERROR)
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#endif // MBED_OSPI_FLASH_MX25LM51245G_H

‎TESTS/mbed_hal/ospi/flash_configs/flash_configs.h

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/* mbed Microcontroller Library
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* Copyright (c) 2018-2020 ARM Limited
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_FLASH_CONFIGS_H
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#define MBED_FLASH_CONFIGS_H
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#if defined(TARGET_MX25LM51245G)
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#include "MX25LM51245G_config.h"
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#endif
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#endif // MBED_FLASH_CONFIGS_H
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