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Merge pull request #11434 from romanjoe/pr/cy8ckit_064s2_4343w
Initial addition of files to support CY8CKIT_064S2_4343W target
2 parents 734072f + 27f9cf8 commit 9c82706

40 files changed

+11742
-24
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‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

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/*******************************************************************************
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* File Name: cycfg.c
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*
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* Description:
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* Wrapper function to initialize all generated code.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg.h"
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void init_cycfg_all(void)
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{
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init_cycfg_system();
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init_cycfg_clocks();
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init_cycfg_dmas();
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init_cycfg_routing();
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init_cycfg_peripherals();
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init_cycfg_pins();
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}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

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/*******************************************************************************
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* File Name: cycfg.h
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*
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* Description:
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* Simple wrapper header containing all generated files.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_H)
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#define CYCFG_H
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#include "cycfg_notices.h"
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#include "cycfg_system.h"
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#include "cycfg_clocks.h"
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#include "cycfg_dmas.h"
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#include "cycfg_routing.h"
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#include "cycfg_peripherals.h"
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#include "cycfg_pins.h"
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void init_cycfg_all(void);
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#if defined(__cplusplus)
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}
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#endif
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#endif /* CYCFG_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

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/*******************************************************************************
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* File Name: cycfg.timestamp
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*
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* Description:
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* Sentinel file for determining if generated source is up to date.
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

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/*******************************************************************************
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* File Name: cycfg_clocks.c
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*
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* Description:
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* Clock configuration
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_clocks.h"
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj =
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{
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.type = CYHAL_RSC_CLOCK,
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.block_num = CYBSP_USB_CLK_DIV_HW,
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.channel_num = CYBSP_USB_CLK_DIV_NUM,
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};
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj =
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{
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.type = CYHAL_RSC_CLOCK,
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.block_num = CYBSP_SDIO_DIV_HW,
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.channel_num = CYBSP_SDIO_DIV_NUM,
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};
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj =
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{
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.type = CYHAL_RSC_CLOCK,
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.block_num = CYBSP_CSD_COMM_CLK_DIV_HW,
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.channel_num = CYBSP_CSD_COMM_CLK_DIV_NUM,
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};
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
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{
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.type = CYHAL_RSC_CLOCK,
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.block_num = CYBSP_CSD_CLK_DIV_HW,
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.channel_num = CYBSP_CSD_CLK_DIV_NUM,
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};
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t peri_0_div_8_4_obj =
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{
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.type = CYHAL_RSC_CLOCK,
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.block_num = peri_0_div_8_4_HW,
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.channel_num = peri_0_div_8_4_NUM,
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};
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#endif //defined (CY_USING_HAL)
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void init_cycfg_clocks(void)
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{
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 999U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_USB_CLK_DIV_obj);
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#endif //defined (CY_USING_HAL)
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_SDIO_DIV_obj);
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#endif //defined (CY_USING_HAL)
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_CSD_COMM_CLK_DIV_obj);
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#endif //defined (CY_USING_HAL)
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
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#endif //defined (CY_USING_HAL)
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 4U, 108U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 4U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&peri_0_div_8_4_obj);
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#endif //defined (CY_USING_HAL)
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}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

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/*******************************************************************************
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* File Name: cycfg_clocks.h
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*
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* Description:
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* Clock configuration
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* This file was automatically generated and should not be modified.
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_CLOCKS_H)
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#define CYCFG_CLOCKS_H
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#include "cycfg_notices.h"
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#include "cy_sysclk.h"
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#if defined (CY_USING_HAL)
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#include "cyhal_hwmgr.h"
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#endif //defined (CY_USING_HAL)
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define CYBSP_USB_CLK_DIV_ENABLED 1U
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#define CYBSP_USB_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
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#define CYBSP_USB_CLK_DIV_NUM 0U
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#define CYBSP_SDIO_DIV_ENABLED 1U
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#define CYBSP_SDIO_DIV_HW CY_SYSCLK_DIV_8_BIT
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#define CYBSP_SDIO_DIV_NUM 0U
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#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
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#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
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#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
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#define CYBSP_CSD_CLK_DIV_ENABLED 1U
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#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
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#define CYBSP_CSD_CLK_DIV_NUM 3U
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#define peri_0_div_8_4_ENABLED 1U
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#define peri_0_div_8_4_HW CY_SYSCLK_DIV_8_BIT
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#define peri_0_div_8_4_NUM 4U
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#if defined (CY_USING_HAL)
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extern const cyhal_resource_inst_t CYBSP_USB_CLK_DIV_obj;
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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extern const cyhal_resource_inst_t CYBSP_SDIO_DIV_obj;
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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extern const cyhal_resource_inst_t CYBSP_CSD_COMM_CLK_DIV_obj;
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
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#endif //defined (CY_USING_HAL)
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#if defined (CY_USING_HAL)
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extern const cyhal_resource_inst_t peri_0_div_8_4_obj;
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#endif //defined (CY_USING_HAL)
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void init_cycfg_clocks(void);
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#if defined(__cplusplus)
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}
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#endif
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#endif /* CYCFG_CLOCKS_H */

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