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Merge pull request #949 from GustavWi/iar_mbed
IAR support LPC824
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‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/LPC824.icf

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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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/*-Specials-*/
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define symbol __ICFEDIT_intvec_start__ = 0x00000000;
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
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define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF;
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define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000;
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define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF;
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define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0;
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define symbol __ICFEDIT_region_RAM_end__ = 0x10001FFF;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = 0x400;
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define symbol __ICFEDIT_size_heap__ = 0xA00;
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/**** End of ICF editor section. ###ICF###*/
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define symbol __CRP_start__ = 0x000002FC;
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define symbol __CRP_end__ = 0x000002FF;
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__];
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define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
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define region CRP_region = mem:[from __CRP_start__ to __CRP_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place in RAM_region { readwrite,
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block HEAP, block CSTACK };
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place in CRP_region { section .crp };

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/TOOLCHAIN_IAR/startup_LPC8xx.s

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/**************************************************
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*
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* Part one of the system initialization code, contains low-level
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* initialization, plain thumb variant.
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*
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* Copyright 2011 IAR Systems. All rights reserved.
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*
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* $Revision: 47876 $
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*
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**************************************************/
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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PUBLIC __vector_table_0x1c
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PUBLIC __Vectors
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PUBLIC __Vectors_End
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PUBLIC __Vectors_Size
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler
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DCD NMI_Handler
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DCD HardFault_Handler
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DCD 0
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DCD 0
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DCD 0
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__vector_table_0x1c
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DCD 0
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DCD 0
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DCD 0
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DCD 0
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DCD SVC_Handler
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DCD 0
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DCD 0
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DCD PendSV_Handler
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DCD SysTick_Handler
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; External Interrupts
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DCD SPI0_IRQHandler ; SPI0 controller
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DCD SPI1_IRQHandler ; SPI1 controller
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DCD 0 ; Reserved
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DCD UART0_IRQHandler ; UART0
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DCD UART1_IRQHandler ; UART1
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DCD UART2_IRQHandler ; UART2
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DCD 0 ; Reserved
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DCD I2C1_IRQHandler ; I2C1 controller
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DCD I2C0_IRQHandler ; I2C0 controller
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DCD SCT_IRQHandler ; Smart Counter Timer
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DCD MRT_IRQHandler ; Multi-Rate Timer
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DCD CMP_IRQHandler ; Comparator
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DCD WDT_IRQHandler ; PIO1 (0:11)
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DCD BOD_IRQHandler ; Brown Out Detect
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DCD Flash_IRQHandler ; Flash interrupt
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DCD WKT_IRQHandler ; Wakeup timer
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DCD ADC_SEQA_IRQHandler ; ADC sequence A completion
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DCD ADC_SEQB_IRQHandler ; ADC sequence B completion
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DCD ADC_THCMP_IRQHandler ; ADC threshold compare
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DCD ADC_OVR_IRQHandler ; ADC overrun
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DCD DMA__RQHandler ; DMA interrupt
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DCD I2C2_IRQHandler ; I2C2 controller
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DCD I2C3_IRQHandler ; I2C3 controller
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DCD 0 ; Reserved
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DCD PININT0_IRQHandler ; PIO INT0
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DCD PININT1_IRQHandler ; PIO INT1
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DCD PININT2_IRQHandler ; PIO INT2
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DCD PININT3_IRQHandler ; PIO INT3
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DCD PININT4_IRQHandler ; PIO INT4
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DCD PININT5_IRQHandler ; PIO INT5
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DCD PININT6_IRQHandler ; PIO INT6
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DCD PININT7_IRQHandler ; PIO INT7
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__Vectors_End
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__Vectors EQU __vector_table
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__Vectors_Size EQU __Vectors_End - __Vectors
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:NOROOT:REORDER(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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PUBWEAK HardFault_Handler
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PUBWEAK SVC_Handler
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PUBWEAK PendSV_Handler
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PUBWEAK SysTick_Handler
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PUBWEAK SPI0_IRQHandler
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PUBWEAK SPI1_IRQHandler
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PUBWEAK UART0_IRQHandler
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PUBWEAK UART1_IRQHandler
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PUBWEAK UART2_IRQHandler
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PUBWEAK I2C1_IRQHandler
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PUBWEAK I2C0_IRQHandler
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PUBWEAK SCT_IRQHandler
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PUBWEAK MRT_IRQHandler
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PUBWEAK CMP_IRQHandler
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PUBWEAK WDT_IRQHandler
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PUBWEAK BOD_IRQHandler
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PUBWEAK Flash_IRQHandler
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PUBWEAK WKT_IRQHandler
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PUBWEAK ADC_SEQA_IRQHandler
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PUBWEAK ADC_SEQB_IRQHandler
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PUBWEAK ADC_THCMP_IRQHandler
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PUBWEAK ADC_OVR_IRQHandler
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PUBWEAK DMA__RQHandler
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PUBWEAK I2C2_IRQHandler
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PUBWEAK I2C3_IRQHandler
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PUBWEAK PININT0_IRQHandler
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PUBWEAK PININT1_IRQHandler
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PUBWEAK PININT2_IRQHandler
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PUBWEAK PININT3_IRQHandler
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PUBWEAK PININT4_IRQHandler
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PUBWEAK PININT5_IRQHandler
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PUBWEAK PININT6_IRQHandler
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PUBWEAK PININT7_IRQHandler
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SECTION .text:CODE:REORDER:NOROOT(1)
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THUMB
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NMI_Handler
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HardFault_Handler
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SVC_Handler
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PendSV_Handler
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SysTick_Handler
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SPI0_IRQHandler
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SPI1_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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I2C1_IRQHandler
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I2C0_IRQHandler
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SCT_IRQHandler
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MRT_IRQHandler
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CMP_IRQHandler
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WDT_IRQHandler
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BOD_IRQHandler
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Flash_IRQHandler
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WKT_IRQHandler
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ADC_SEQA_IRQHandler
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ADC_SEQB_IRQHandler
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ADC_THCMP_IRQHandler
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ADC_OVR_IRQHandler
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DMA__RQHandler
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I2C2_IRQHandler
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I2C3_IRQHandler
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PININT0_IRQHandler
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PININT1_IRQHandler
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PININT2_IRQHandler
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PININT3_IRQHandler
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PININT4_IRQHandler
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PININT5_IRQHandler
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PININT6_IRQHandler
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PININT7_IRQHandler
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Default_IRQHandler
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B Default_IRQHandler
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SECTION .crp:CODE:ROOT(2)
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DATA
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/* Code Read Protection
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NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode
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CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
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- Copy RAM to flash command can not write to Sector 0.
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- Erase command can erase Sector 0 only when all sectors
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are selected for erase.
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- Compare command is disabled.
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- Read Memory command is disabled.
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CRP2 0x87654321 - Read Memory is disabled.
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- Write to RAM is disabled.
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- "Go" command is disabled.
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- Copy RAM to flash is disabled.
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- Compare is disabled.
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CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
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by pulling PIO0_1 LOW is disabled if a valid user code is
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present in flash sector 0.
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Caution: If CRP3 is selected, no future factory testing can be
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performed on the device.
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*/
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DCD 0xFFFFFFFF
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END

‎workspace_tools/build_release.py

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('ARCH_PRO', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')),
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('LPC2368', ('ARM', 'GCC_ARM')),
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('LPC812', ('uARM','IAR')),
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('LPC824', ('uARM',)),
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('LPC824', ('uARM', 'IAR')),
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('SSCI824', ('uARM',)),
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('LPC1347', ('ARM','IAR')),
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('LPC4088', ('ARM', 'GCC_ARM', 'GCC_CR', 'IAR')),

‎workspace_tools/export/iar.py

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'LPC812',
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'LPC4088',
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'LPC4088_DM',
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'LPC824',
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'UBLOX_C027',
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'ARCH_PRO',
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'K20D50M',

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