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Merge pull request #11887 from kyle-cypress/pr/target-p62s1-43438
Add target for CYW9P62S1_43438EVB_01
2 parents 860f18b + 1a0925e commit a169edf

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‎features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/COMPONENT_43438/w_bt_firmware_controller.c

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‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

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/*******************************************************************************
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* File Name: cycfg.c
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*
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* Description:
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* Wrapper function to initialize all generated code.
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg.h"
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void init_cycfg_all(void)
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{
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init_cycfg_system();
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init_cycfg_clocks();
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init_cycfg_routing();
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init_cycfg_peripherals();
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init_cycfg_pins();
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}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

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/*******************************************************************************
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* File Name: cycfg.h
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*
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* Description:
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* Simple wrapper header containing all generated files.
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_H)
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#define CYCFG_H
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#include "cycfg_notices.h"
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#include "cycfg_system.h"
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#include "cycfg_clocks.h"
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#include "cycfg_routing.h"
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#include "cycfg_peripherals.h"
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#include "cycfg_pins.h"
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void init_cycfg_all(void);
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#if defined(__cplusplus)
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}
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#endif
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#endif /* CYCFG_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

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/*******************************************************************************
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* File Name: cycfg.timestamp
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*
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* Description:
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* Sentinel file for determining if generated source is up to date.
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

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/*******************************************************************************
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* File Name: cycfg_clocks.c
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*
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* Description:
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* Clock configuration
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_clocks.h"
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
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{
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.type = CYHAL_RSC_CLOCK,
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.block_num = CYBSP_CSD_CLK_DIV_HW,
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.channel_num = CYBSP_CSD_CLK_DIV_NUM,
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};
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#endif //defined (CY_USING_HAL)
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void init_cycfg_clocks(void)
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{
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
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#endif //defined (CY_USING_HAL)
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}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

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/*******************************************************************************
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* File Name: cycfg_clocks.h
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*
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* Description:
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* Clock configuration
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_CLOCKS_H)
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#define CYCFG_CLOCKS_H
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#include "cycfg_notices.h"
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#include "cy_sysclk.h"
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#if defined (CY_USING_HAL)
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#include "cyhal_hwmgr.h"
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#endif //defined (CY_USING_HAL)
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define CYBSP_CSD_CLK_DIV_ENABLED 1U
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#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
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#define CYBSP_CSD_CLK_DIV_NUM 3U
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#if defined (CY_USING_HAL)
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extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;
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#endif //defined (CY_USING_HAL)
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void init_cycfg_clocks(void);
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#if defined(__cplusplus)
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}
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#endif
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#endif /* CYCFG_CLOCKS_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

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/*******************************************************************************
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* File Name: cycfg_notices.h
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*
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* Description:
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* Contains warnings and errors that occurred while generating code for the
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* design.
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_NOTICES_H)
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#define CYCFG_NOTICES_H
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#endif /* CYCFG_NOTICES_H */

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

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/*******************************************************************************
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* File Name: cycfg_peripherals.c
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*
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* Description:
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* Peripheral Hardware Block configuration
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_peripherals.h"
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cy_stc_csd_context_t cy_csd_0_context =
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{
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.lockKey = CY_CSD_NONE_KEY,
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};
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void init_cycfg_peripherals(void)
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{
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Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
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}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

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/*******************************************************************************
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* File Name: cycfg_peripherals.h
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*
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* Description:
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* Peripheral Hardware Block configuration
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* This file was automatically generated and should not be modified.
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* cfg-backend-cli: 1.2.0.1478
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* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#if !defined(CYCFG_PERIPHERALS_H)
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#define CYCFG_PERIPHERALS_H
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#include "cycfg_notices.h"
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#include "cy_sysclk.h"
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#include "cy_csd.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define CYBSP_CSD_ENABLED 1U
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#define CY_CAPSENSE_CORE 4u
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#define CY_CAPSENSE_CPU_CLK 100000000u
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#define CY_CAPSENSE_PERI_CLK 100000000u
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#define CY_CAPSENSE_VDDA_MV 3300u
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#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
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#define CY_CAPSENSE_PERI_DIV_INDEX 3u
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#define Cmod_PORT GPIO_PRT7
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#define CintA_PORT GPIO_PRT7
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#define CintB_PORT GPIO_PRT7
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#define Button0_Rx0_PORT GPIO_PRT1
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#define Button0_Tx_PORT GPIO_PRT8
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#define Button1_Rx0_PORT GPIO_PRT1
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#define Button1_Tx_PORT GPIO_PRT8
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#define LinearSlider0_Sns0_PORT GPIO_PRT8
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#define LinearSlider0_Sns1_PORT GPIO_PRT8
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#define LinearSlider0_Sns2_PORT GPIO_PRT8
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#define LinearSlider0_Sns3_PORT GPIO_PRT8
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#define LinearSlider0_Sns4_PORT GPIO_PRT8
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#define Cmod_PIN 7u
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#define CintA_PIN 1u
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#define CintB_PIN 2u
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#define Button0_Rx0_PIN 0u
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#define Button0_Tx_PIN 1u
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#define Button1_Rx0_PIN 0u
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#define Button1_Tx_PIN 2u
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#define LinearSlider0_Sns0_PIN 3u
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#define LinearSlider0_Sns1_PIN 4u
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#define LinearSlider0_Sns2_PIN 5u
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#define LinearSlider0_Sns3_PIN 6u
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#define LinearSlider0_Sns4_PIN 7u
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#define Cmod_PORT_NUM 7u
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#define CintA_PORT_NUM 7u
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#define CintB_PORT_NUM 7u
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#define CYBSP_CSD_HW CSD0
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#define CYBSP_CSD_IRQ csd_interrupt_IRQn
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extern cy_stc_csd_context_t cy_csd_0_context;
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void init_cycfg_peripherals(void);
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#if defined(__cplusplus)
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}
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#endif
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#endif /* CYCFG_PERIPHERALS_H */

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