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Cruz Monrreal IICruz Monrreal II
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Added missing astyle corrections for usb/device/targets/*
1 parent da20839 commit a1c047a

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10 files changed

+132
-127
lines changed

10 files changed

+132
-127
lines changed

usb/device/targets/TARGET_Freescale/USBPhyHw.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ class USBPhyHw : public USBPhy {
3636
virtual void sof_disable();
3737
virtual void set_address(uint8_t address);
3838
virtual void remote_wakeup();
39-
virtual const usb_ep_table_t* endpoint_table();
39+
virtual const usb_ep_table_t *endpoint_table();
4040

4141
virtual uint32_t ep0_set_max_packet(uint32_t max_packet);
4242
virtual void ep0_setup_read_result(uint8_t *buffer, uint32_t size);

usb/device/targets/TARGET_Freescale/USBPhy_Kinetis.cpp

Lines changed: 32 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ typedef enum {
8383
// * as there are ODD and EVEN buffer -> 8*2 bdt
8484
MBED_ALIGN(512) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2]; // 512 bytes aligned!
8585

86-
uint8_t * endpoint_buffer[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
86+
uint8_t *endpoint_buffer[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
8787
uint8_t ep0_buffer[2][MAX_PACKET_SIZE_EP0];
8888
uint8_t ep1_buffer[2][MAX_PACKET_SIZE_EP1];
8989
uint8_t ep2_buffer[2][MAX_PACKET_SIZE_EP2];
@@ -96,8 +96,9 @@ static ctrl_xfer_t ctrl_xfer = CTRL_XFER_READY;
9696

9797
static uint32_t Data1 = 0x55555555;
9898

99-
static uint32_t frameNumber() {
100-
return((USB0->FRMNUML | (USB0->FRMNUMH << 8)) & 0x07FF);
99+
static uint32_t frameNumber()
100+
{
101+
return ((USB0->FRMNUML | (USB0->FRMNUMH << 8)) & 0x07FF);
101102
}
102103

103104
USBPhy *get_usb_phy()
@@ -126,11 +127,11 @@ void USBPhyHw::init(USBPhyEvents *events)
126127
NVIC_DisableIRQ(USB0_IRQn);
127128

128129
#if (defined(FSL_FEATURE_SOC_MPU_COUNT) && (FSL_FEATURE_SOC_MPU_COUNT > 0U))
129-
MPU->CESR=0;
130+
MPU->CESR = 0;
130131
#endif
131132

132133
#if (defined(FSL_FEATURE_SOC_SYSMPU_COUNT) && (FSL_FEATURE_SOC_SYSMPU_COUNT > 0U))
133-
SYSMPU->CESR=0;
134+
SYSMPU->CESR = 0;
134135
#endif
135136

136137
#if defined(TARGET_KL43Z) || defined(TARGET_K22F) || defined(TARGET_K64F)
@@ -150,9 +151,9 @@ void USBPhyHw::init(USBPhyEvents *events)
150151

151152
// USB Module Configuration
152153
// Set BDT Base Register
153-
USB0->BDTPAGE1 = (uint8_t)((uint32_t)bdt>>8);
154-
USB0->BDTPAGE2 = (uint8_t)((uint32_t)bdt>>16);
155-
USB0->BDTPAGE3 = (uint8_t)((uint32_t)bdt>>24);
154+
USB0->BDTPAGE1 = (uint8_t)((uint32_t)bdt >> 8);
155+
USB0->BDTPAGE2 = (uint8_t)((uint32_t)bdt >> 16);
156+
USB0->BDTPAGE3 = (uint8_t)((uint32_t)bdt >> 24);
156157

157158
// Clear interrupt flag
158159
USB0->ISTAT = 0xff;
@@ -209,7 +210,7 @@ void USBPhyHw::connect()
209210
void USBPhyHw::disconnect()
210211
{
211212
// disable all endpoints to prevent them from nacking when disconnected
212-
for(int i = 0; i < 16; i++) {
213+
for (int i = 0; i < 16; i++) {
213214
USB0->ENDPOINT[i].ENDPT = 0x00;
214215
}
215216
// disable USB
@@ -259,7 +260,7 @@ void USBPhyHw::remote_wakeup()
259260
#define ALLOW_BULK_OR_INT_ENDPOINTS (USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_ALLOW_INT)
260261
#define ALLOW_NO_ENDPOINTS 0
261262

262-
const usb_ep_table_t* USBPhyHw::endpoint_table()
263+
const usb_ep_table_t *USBPhyHw::endpoint_table()
263264
{
264265
static const usb_ep_table_t endpoint_table = {
265266
1, // No cost per endpoint - everything allocated up front
@@ -349,7 +350,7 @@ void USBPhyHw::ep0_write(uint8_t *buffer, uint32_t size)
349350
// Prepare for next setup packet
350351
endpoint_read_core(EP0OUT, MAX_PACKET_SIZE_EP0);
351352
ctrl_xfer = CTRL_XFER_READY;
352-
}
353+
}
353354
endpoint_write(EP0IN, buffer, size);
354355

355356
// Clear suspend after the setup stage
@@ -386,7 +387,7 @@ void USBPhyHw::ep0_stall()
386387
bool USBPhyHw::endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type)
387388
{
388389
uint32_t handshake_flag = 0;
389-
uint8_t * buf;
390+
uint8_t *buf;
390391

391392
if (DESC_TO_PHY(endpoint) > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
392393
return false;
@@ -406,21 +407,21 @@ bool USBPhyHw::endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_
406407

407408
// IN endpt -> device to host (TX)
408409
if (DESC_EP_IN(endpoint)) {
409-
bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].address = (uint32_t) buf;
410-
bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].info = 0;
410+
bdt[EP_BDT_IDX(log_endpoint, TX, ODD)].address = (uint32_t) buf;
411+
bdt[EP_BDT_IDX(log_endpoint, TX, ODD)].info = 0;
411412
bdt[EP_BDT_IDX(log_endpoint, TX, EVEN)].address = 0;
412413
USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
413414
USB_ENDPT_EPTXEN_MASK; // en TX (IN) tran
414415
}
415416
// OUT endpt -> host to device (RX)
416417
else {
417-
bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].byte_count = max_packet;
418-
bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address = (uint32_t) buf;
419-
bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_DTS_MASK;
418+
bdt[EP_BDT_IDX(log_endpoint, RX, ODD)].byte_count = max_packet;
419+
bdt[EP_BDT_IDX(log_endpoint, RX, ODD)].address = (uint32_t) buf;
420+
bdt[EP_BDT_IDX(log_endpoint, RX, ODD)].info = BD_DTS_MASK;
420421
bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info = 0;
421422
if (log_endpoint == 0) {
422423
// Prepare for setup packet
423-
bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info |= BD_OWN_MASK;
424+
bdt[EP_BDT_IDX(log_endpoint, RX, ODD)].info |= BD_OWN_MASK;
424425
}
425426
USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
426427
USB_ENDPT_EPRXEN_MASK; // en RX (OUT) tran.
@@ -466,8 +467,7 @@ bool USBPhyHw::endpoint_read_core(usb_ep_t endpoint, uint32_t max_packet)
466467
bdt[idx].byte_count = max_packet;
467468
if ((Data1 >> DESC_TO_PHY(endpoint)) & 1) {
468469
bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
469-
}
470-
else {
470+
} else {
471471
bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK;
472472
}
473473

@@ -491,7 +491,7 @@ bool USBPhyHw::endpoint_read_result_core(usb_ep_t endpoint, uint8_t *data, uint3
491491
{
492492
uint32_t n, sz, idx, setup = 0;
493493
uint8_t not_iso;
494-
uint8_t * ep_buf;
494+
uint8_t *ep_buf;
495495

496496
uint32_t log_endpoint = DESC_TO_LOG(endpoint);
497497

@@ -542,7 +542,7 @@ bool USBPhyHw::endpoint_read_result_core(usb_ep_t endpoint, uint8_t *data, uint3
542542
bool USBPhyHw::endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size)
543543
{
544544
uint32_t idx, n;
545-
uint8_t * ep_buf;
545+
uint8_t *ep_buf;
546546

547547
if (DESC_TO_PHY(endpoint) > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
548548
return false;
@@ -588,7 +588,7 @@ void USBPhyHw::process()
588588
// reset interrupt
589589
if (istat & USB_ISTAT_USBRST_MASK) {
590590
// disable all endpt
591-
for(i = 0; i < 16; i++) {
591+
for (i = 0; i < 16; i++) {
592592
USB0->ENDPOINT[i].ENDPT = 0x00;
593593
}
594594

@@ -631,9 +631,10 @@ void USBPhyHw::process()
631631
}
632632

633633
// stall interrupt
634-
if (istat & 1<<7) {
635-
if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK)
634+
if (istat & 1 << 7) {
635+
if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK) {
636636
USB0->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
637+
}
637638
USB0->ISTAT = USB_ISTAT_STALL_MASK;
638639
}
639640

@@ -660,9 +661,9 @@ void USBPhyHw::process()
660661
} else {
661662
// OUT packet
662663
if (rx_en && (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == OUT_TOKEN)) {
663-
if (num == 0)
664+
if (num == 0) {
664665
events->ep0_out();
665-
else {
666+
} else {
666667
epComplete |= EP(phy_ep);
667668
events->out(PHY_TO_DESC(phy_ep));
668669
}
@@ -676,8 +677,7 @@ void USBPhyHw::process()
676677
USB0->ADDR = addr & 0x7F;
677678
set_addr = 0;
678679
}
679-
}
680-
else {
680+
} else {
681681
epComplete |= EP(phy_ep);
682682
events->in(PHY_TO_DESC(phy_ep));
683683
}
@@ -688,7 +688,7 @@ void USBPhyHw::process()
688688
}
689689

690690
// sleep interrupt
691-
if (istat & 1<<4) {
691+
if (istat & 1 << 4) {
692692
USB0->ISTAT = USB_ISTAT_SLEEP_MASK;
693693
events->suspend(true);
694694
}
@@ -713,7 +713,8 @@ void USBPhyHw::process()
713713
NVIC_EnableIRQ(USB0_IRQn);
714714
}
715715

716-
void USBPhyHw::_usbisr(void) {
716+
void USBPhyHw::_usbisr(void)
717+
{
717718
NVIC_DisableIRQ(USB0_IRQn);
718719
instance->events->start_process();
719720
}

usb/device/targets/TARGET_NXP/USBHAL_LPC17.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -126,10 +126,10 @@ static USBPhyHw *instance;
126126
static uint32_t opStarted;
127127

128128
static const usb_ep_t ISO_EPS[] = {
129-
0x03, 0x83,
130-
0x06, 0x86,
131-
0x09, 0x89,
132-
0x0C, 0x8C
129+
0x03, 0x83,
130+
0x06, 0x86,
131+
0x09, 0x89,
132+
0x0C, 0x8C
133133
};
134134

135135
static void SIECommand(uint32_t command)
@@ -171,7 +171,7 @@ static uint8_t SIEgetDeviceStatus(void)
171171
return SIEReadData(SIE_CMD_GET_DEVICE_STATUS);
172172
}
173173

174-
void SIEsetAddress(uint8_t address, bool enable=true)
174+
void SIEsetAddress(uint8_t address, bool enable = true)
175175
{
176176
// Write SIE device address register
177177
SIECommand(SIE_CMD_SET_ADDRESS);

usb/device/targets/TARGET_RENESAS/TARGET_RZ_A1XX/USBPhyHw.h

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ class USBPhyHw : public USBPhy {
3737
virtual void sof_disable();
3838
virtual void set_address(uint8_t address);
3939
virtual void remote_wakeup();
40-
virtual const usb_ep_table_t* endpoint_table();
40+
virtual const usb_ep_table_t *endpoint_table();
4141

4242
virtual uint32_t ep0_set_max_packet(uint32_t max_packet);
4343
virtual void ep0_setup_read_result(uint8_t *buffer, uint32_t size);
@@ -59,7 +59,7 @@ class USBPhyHw : public USBPhy {
5959
virtual void process();
6060

6161
private:
62-
#define PIPE_NUM (16)
62+
#define PIPE_NUM (16)
6363

6464
typedef struct {
6565
bool enable;
@@ -76,18 +76,18 @@ class USBPhyHw : public USBPhy {
7676
static void _usbisr(void);
7777
void chg_curpipe(uint16_t pipe, uint16_t isel);
7878
uint16_t is_set_frdy(uint16_t pipe, uint16_t isel);
79-
uint8_t * read_fifo(uint16_t pipe, uint16_t count, uint8_t *read_p);
79+
uint8_t *read_fifo(uint16_t pipe, uint16_t count, uint8_t *read_p);
8080
uint16_t read_data(uint16_t pipe);
8181
void fifo_to_buf(uint16_t pipe);
82-
uint8_t * write_fifo(uint16_t pipe, uint16_t count, uint8_t *write_p);
82+
uint8_t *write_fifo(uint16_t pipe, uint16_t count, uint8_t *write_p);
8383
uint16_t write_data(uint16_t pipe);
8484
void buf_to_fifo(uint16_t pipe);
85-
uint16_t * get_pipectr_reg(uint16_t pipe);
86-
uint16_t * get_pipetre_reg(uint16_t pipe);
87-
uint16_t * get_pipetrn_reg(uint16_t pipe);
88-
uint16_t * get_fifoctr_reg(uint16_t pipe);
89-
uint16_t * get_fifosel_reg(uint16_t pipe);
90-
uint32_t * get_fifo_reg(uint16_t pipe);
85+
uint16_t *get_pipectr_reg(uint16_t pipe);
86+
uint16_t *get_pipetre_reg(uint16_t pipe);
87+
uint16_t *get_pipetrn_reg(uint16_t pipe);
88+
uint16_t *get_fifoctr_reg(uint16_t pipe);
89+
uint16_t *get_fifosel_reg(uint16_t pipe);
90+
uint32_t *get_fifo_reg(uint16_t pipe);
9191
uint16_t get_pid(uint16_t pipe);
9292
void set_mbw(uint16_t pipe, uint16_t data);
9393
void set_pid(uint16_t pipe, uint16_t new_pid);

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