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K64F - SPI - delays are set, pin definition for tests
1 parent 1f3b3ab commit a2b3b53

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1 file changed

+24
-5
lines changed
  • libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F

1 file changed

+24
-5
lines changed

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_K64F/spi_api.c

Lines changed: 24 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -24,25 +24,39 @@
2424
#include "fsl_dspi_hal.h"
2525

2626
static const PinMap PinMap_SPI_SCLK[] = {
27-
27+
{PTD1, SPI_0, 2},
2828
{NC , NC , 0}
2929
};
3030

3131
static const PinMap PinMap_SPI_MOSI[] = {
32-
32+
{PTD2, SPI_0, 2},
3333
{NC , NC , 0}
3434
};
3535

3636
static const PinMap PinMap_SPI_MISO[] = {
37-
37+
{PTD3, SPI_0, 2},
3838
{NC , NC , 0}
3939
};
4040

4141
static const PinMap PinMap_SPI_SSEL[] = {
42-
42+
{PTD0, SPI_0, 2},
4343
{NC , NC , 0}
4444
};
4545

46+
static void spi_set_delays(uint32_t instance) {
47+
dspi_delay_settings_config_t delay_config;
48+
delay_config.pcsToSck = 1; /*!< PCS to SCK delay (CSSCK): initialize the scalar
49+
* value to '1' to provide the master with a little
50+
* more data-in read setup time.
51+
*/
52+
delay_config.pcsToSckPre = 0; /*!< PCS to SCK delay prescalar (PCSSCK) */
53+
delay_config.afterSckPre = 0; /*!< After SCK delay prescalar (PASC)*/
54+
delay_config.afterSck = 0; /*!< After SCK delay scalar (ASC)*/
55+
delay_config.afterTransferPre = 0; /*!< Delay after transfer prescalar (PDT)*/
56+
delay_config.afterTransfer = 0;
57+
dspi_hal_configure_delays(instance, kDspiCtar0, &delay_config);
58+
}
59+
4660
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
4761
// determine the SPI to use
4862
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
@@ -67,9 +81,11 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
6781
} else {
6882
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
6983
}
84+
spi_set_delays(obj->instance);
7085
spi_frequency(obj, 1000000);
7186

7287
dspi_hal_enable(obj->instance);
88+
dspi_hal_start_transfer(obj->instance);
7389

7490
// pin out the spi pins
7591
pinmap_pinout(mosi, PinMap_SPI_MOSI);
@@ -104,7 +120,7 @@ void spi_format(spi_t *obj, int bits, int mode, int slave) {
104120
void spi_frequency(spi_t *obj, int hz) {
105121
uint32_t busClock;
106122
clock_manager_get_frequency(kBusClock, &busClock);
107-
dspi_hal_set_baud(obj->instance, kDspiCtar0, hz, busClock);
123+
dspi_hal_set_baud(obj->instance, kDspiCtar0, (uint32_t)hz, busClock);
108124
}
109125

110126
static inline int spi_writeable(spi_t * obj) {
@@ -120,10 +136,13 @@ int spi_master_write(spi_t *obj, int value) {
120136
while(!spi_writeable(obj));
121137
dspi_command_config_t command = {0};
122138
command.isEndOfQueue = true;
139+
command.isChipSelectContinuous = 0;
123140
dspi_hal_write_data_master_mode(obj->instance, &command, (uint16_t)value);
141+
dspi_hal_clear_status_flag(obj->instance, kDspiTxFifoFillRequest);
124142

125143
// wait rx buffer full
126144
while (!spi_readable(obj));
145+
dspi_hal_clear_status_flag(obj->instance, kDspiRxFifoDrainRequest);
127146
return dspi_hal_read_data(obj->instance) & 0xff;
128147
}
129148

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