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29 | 29 | #if DEVICE_ANALOGIN
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30 | 30 | MBED_WEAK const PinMap PinMap_ADC[] = {
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31 | 31 | #if ADC0_BASE
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32 |
| - {PA0, ADC_0, adcPosSelAPORT3XCH8}, |
33 |
| - {PA1, ADC_0, adcPosSelAPORT4XCH9}, |
34 |
| - {PA2, ADC_0, adcPosSelAPORT3XCH10}, |
35 |
| - {PA3, ADC_0, adcPosSelAPORT4XCH11}, |
36 |
| - {PA4, ADC_0, adcPosSelAPORT3XCH12}, |
37 |
| - {PA5, ADC_0, adcPosSelAPORT4XCH13}, |
| 32 | + {PA0, ADC_0, adcPosSelAPORT1XCH0}, |
| 33 | + {PA1, ADC_0, adcPosSelAPORT2XCH1}, |
| 34 | + {PA2, ADC_0, adcPosSelAPORT1XCH2}, |
| 35 | + {PA3, ADC_0, adcPosSelAPORT2XCH3}, |
| 36 | + {PA4, ADC_0, adcPosSelAPORT1XCH4}, |
| 37 | + {PA5, ADC_0, adcPosSelAPORT2XCH5}, |
| 38 | + {PA6, ADC_0, adcPosSelAPORT1XCH6}, |
| 39 | + {PA7, ADC_0, adcPosSelAPORT2XCH7}, |
| 40 | + {PA8, ADC_0, adcPosSelAPORT1XCH8}, |
| 41 | + {PA9, ADC_0, adcPosSelAPORT2XCH9}, |
| 42 | + {PA10, ADC_0, adcPosSelAPORT1XCH10}, |
| 43 | + {PA11, ADC_0, adcPosSelAPORT2XCH11}, |
| 44 | + {PA12, ADC_0, adcPosSelAPORT1XCH12}, |
| 45 | + {PA13, ADC_0, adcPosSelAPORT2XCH13}, |
| 46 | + {PA14, ADC_0, adcPosSelAPORT1XCH14}, |
| 47 | + {PA15, ADC_0, adcPosSelAPORT2XCH15}, |
38 | 48 |
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39 |
| - {PB11, ADC_0, adcPosSelAPORT4XCH27}, |
40 |
| - {PB12, ADC_0, adcPosSelAPORT3XCH28}, |
41 |
| - {PB14, ADC_0, adcPosSelAPORT3XCH30}, |
42 |
| - {PB15, ADC_0, adcPosSelAPORT4XCH31}, |
| 49 | + {PB0, ADC_0, adcPosSelAPORT1XCH16}, |
| 50 | + {PB1, ADC_0, adcPosSelAPORT2XCH17}, |
| 51 | + {PB2, ADC_0, adcPosSelAPORT1XCH18}, |
| 52 | + {PB3, ADC_0, adcPosSelAPORT2XCH19}, |
| 53 | + {PB4, ADC_0, adcPosSelAPORT1XCH20}, |
| 54 | + {PB5, ADC_0, adcPosSelAPORT2XCH21}, |
| 55 | + {PB6, ADC_0, adcPosSelAPORT1XCH22}, |
43 | 56 |
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44 |
| - {PC6, ADC_0, adcPosSelAPORT1XCH6}, |
45 |
| - {PC7, ADC_0, adcPosSelAPORT2XCH7}, |
46 |
| - {PC8, ADC_0, adcPosSelAPORT1XCH8}, |
47 |
| - {PC9, ADC_0, adcPosSelAPORT2XCH9}, |
48 |
| - {PC10, ADC_0, adcPosSelAPORT1XCH10}, |
49 |
| - {PC11, ADC_0, adcPosSelAPORT2XCH11}, |
| 57 | + {PB9, ADC_0, adcPosSelAPORT2XCH25}, |
| 58 | + {PB10, ADC_0, adcPosSelAPORT1XCH26}, |
| 59 | + {PB11, ADC_0, adcPosSelAPORT2XCH27}, |
| 60 | + {PB12, ADC_0, adcPosSelAPORT1XCH28}, |
| 61 | + {PB14, ADC_0, adcPosSelAPORT1XCH30}, |
| 62 | + {PB15, ADC_0, adcPosSelAPORT2XCH31}, |
50 | 63 |
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51 |
| - {PD9, ADC_0, adcPosSelAPORT4XCH1}, |
52 |
| - {PD10, ADC_0, adcPosSelAPORT3XCH2}, |
53 |
| - {PD11, ADC_0, adcPosSelAPORT3YCH3}, |
54 |
| - {PD12, ADC_0, adcPosSelAPORT3XCH4}, |
55 |
| - {PD13, ADC_0, adcPosSelAPORT3YCH5}, |
56 |
| - {PD14, ADC_0, adcPosSelAPORT3XCH6}, |
57 |
| - {PD15, ADC_0, adcPosSelAPORT4XCH7}, |
| 64 | + {PD0, ADC_0, adcPosSelAPORT0XCH0}, |
| 65 | + {PD1, ADC_0, adcPosSelAPORT0XCH1}, |
| 66 | + {PD2, ADC_0, adcPosSelAPORT0XCH2}, |
| 67 | + {PD3, ADC_0, adcPosSelAPORT0XCH3}, |
| 68 | + {PD4, ADC_0, adcPosSelAPORT0XCH4}, |
| 69 | + {PD5, ADC_0, adcPosSelAPORT0XCH5}, |
| 70 | + {PD6, ADC_0, adcPosSelAPORT0XCH6}, |
| 71 | + {PD7, ADC_0, adcPosSelAPORT0XCH7}, |
58 | 72 |
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59 |
| - {PF0, ADC_0, adcPosSelAPORT1XCH16}, |
60 |
| - {PF1, ADC_0, adcPosSelAPORT2XCH17}, |
61 |
| - {PF2, ADC_0, adcPosSelAPORT1XCH18}, |
62 |
| - {PF3, ADC_0, adcPosSelAPORT2XCH19}, |
63 |
| - {PF4, ADC_0, adcPosSelAPORT1XCH20}, |
64 |
| - {PF5, ADC_0, adcPosSelAPORT2XCH21}, |
65 |
| - {PF6, ADC_0, adcPosSelAPORT1XCH22}, |
66 |
| - {PF7, ADC_0, adcPosSelAPORT2XCH23}, |
| 73 | + {PE0, ADC_0, adcPosSelAPORT3XCH0}, |
| 74 | + {PE1, ADC_0, adcPosSelAPORT4XCH1}, |
| 75 | + {PE4, ADC_0, adcPosSelAPORT3XCH4}, |
| 76 | + {PE5, ADC_0, adcPosSelAPORT4XCH5}, |
| 77 | + {PE6, ADC_0, adcPosSelAPORT3XCH6}, |
| 78 | + {PE7, ADC_0, adcPosSelAPORT4XCH7}, |
| 79 | + {PE8, ADC_0, adcPosSelAPORT3XCH8}, |
| 80 | + {PE9, ADC_0, adcPosSelAPORT4XCH9}, |
| 81 | + {PE10, ADC_0, adcPosSelAPORT3XCH10}, |
| 82 | + {PE11, ADC_0, adcPosSelAPORT4XCH11}, |
| 83 | + {PE12, ADC_0, adcPosSelAPORT3XCH12}, |
| 84 | + {PE13, ADC_0, adcPosSelAPORT4XCH13}, |
| 85 | + {PE14, ADC_0, adcPosSelAPORT3XCH14}, |
| 86 | + {PE15, ADC_0, adcPosSelAPORT4XCH15}, |
| 87 | + |
| 88 | + {PF0, ADC_0, adcPosSelAPORT3XCH16}, |
| 89 | + {PF1, ADC_0, adcPosSelAPORT4XCH17}, |
| 90 | + {PF2, ADC_0, adcPosSelAPORT3XCH18}, |
| 91 | + {PF3, ADC_0, adcPosSelAPORT4XCH19}, |
| 92 | + {PF4, ADC_0, adcPosSelAPORT3XCH20}, |
| 93 | + {PF5, ADC_0, adcPosSelAPORT4XCH21}, |
| 94 | + {PF6, ADC_0, adcPosSelAPORT3XCH22}, |
| 95 | + {PF7, ADC_0, adcPosSelAPORT4XCH23}, |
| 96 | + {PF8, ADC_0, adcPosSelAPORT3XCH24}, |
| 97 | + {PF9, ADC_0, adcPosSelAPORT4XCH25}, |
| 98 | + {PF10, ADC_0, adcPosSelAPORT3XCH26}, |
| 99 | + {PF11, ADC_0, adcPosSelAPORT4XCH27}, |
| 100 | + {PF12, ADC_0, adcPosSelAPORT3XCH28}, |
| 101 | + {PF13, ADC_0, adcPosSelAPORT4XCH31}, |
| 102 | + {PF14, ADC_0, adcPosSelAPORT3XCH30}, |
| 103 | + {PF15, ADC_0, adcPosSelAPORT4XCH31}, |
67 | 104 | #endif
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68 | 105 | {NC , NC , NC}
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69 | 106 | };
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