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M2351: Support IAR
1. Enable IAR on non-secure targets 2. Disable IAR on secure targets because: (1) IAR toolchain bug: As of IAR 8.32, cmse_nonsecure_caller() is not always inlined. (2) TFM hasn't supported IAR yet.
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‎targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_NS/device/TOOLCHAIN_IAR/M2351.icf

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/*
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* Copyright (c) 2018-2019, Nuvoton Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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include "../../../device/partition_M2351_mem.icf.h";
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if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
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define symbol MBED_BOOT_STACK_SIZE = 0x400;
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}
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/*-Specials-*/
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define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
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define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
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define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
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define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
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define symbol __ICFEDIT_size_intvec__ = 4 * (16 + 102);
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define symbol __ICFEDIT_size_heap__ = 0x400;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
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/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
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define block IRAMVEC with alignment = 1024, size = __ICFEDIT_size_intvec__ { };
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place at start of IRAM_region { block CSTACK };
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place in IRAM_region { block IRAMVEC };
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place in IRAM_region { readwrite };
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place in IRAM_region { block HEAP };

‎targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_S/device/TOOLCHAIN_IAR/M2351.icf

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/*
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* Copyright (c) 2018-2019, Nuvoton Technology Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*###ICF### Section handled by ICF editor, don't touch! ****/
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/*-Editor annotation file-*/
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/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
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include "../../../device/partition_M2351_mem.icf.h";
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if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) {
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define symbol MBED_BOOT_STACK_SIZE = 0x400;
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}
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/* FIXME: Check NSC area requirement */
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/*-Specials-*/
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define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
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/*-Memory Regions-*/
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define symbol __ICFEDIT_region_ROM_start__ = MBED_APP_START;
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define symbol __ICFEDIT_region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
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define symbol __ICFEDIT_region_IRAM_start__ = MBED_RAM_APP_START;
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define symbol __ICFEDIT_region_IRAM_end__ = MBED_RAM_APP_START + MBED_RAM_APP_SIZE - 1;
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/*-Sizes-*/
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define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE;
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define symbol __ICFEDIT_size_intvec__ = 4 * (16 + 102);
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define symbol __ICFEDIT_size_heap__ = 0x400;
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/**** End of ICF editor section. ###ICF###*/
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define memory mem with size = 4G;
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define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
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define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
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/* IAR has something wrong with "$$" in section/block name. So unlike other toolchains,
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* we name "ER_IROM_NSC" instead of "Image$$ER_IROM_NSC". */
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define block ER_IROM_NSC with alignment = 32 { readonly section Veneer$$CMSE };
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define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
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define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
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/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
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define block IRAMVEC with alignment = 1024, size = __ICFEDIT_size_intvec__ { };
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initialize by copy { readwrite };
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do not initialize { section .noinit };
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place at address mem: __ICFEDIT_intvec_start__ { readonly section .intvec };
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place in ROM_region { readonly };
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place at address mem: NU_TZ_NSC_START { block ER_IROM_NSC };
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place at start of IRAM_region { block CSTACK };
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place in IRAM_region { block IRAMVEC };
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place in IRAM_region { readwrite };
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place in IRAM_region { block HEAP };
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define exported symbol Image$$ER_IROM_NSC$$Base = NU_TZ_NSC_START;

‎targets/targets.json

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"inherits": ["NU_PFM_M2351"],
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"core": "Cortex-M23-NS",
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"trustzone": true,
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"supported_toolchains": ["ARMC6", "GCC_ARM"],
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"supported_toolchains": ["ARMC6", "GCC_ARM", "IAR"],
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"extra_labels_add": [
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"M23_NS",
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"NU_PREBUILD_SECURE"

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