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[LPC1114]: uARM fixed
Tested with only "[ 32] MBED_11: Ticker"
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  • libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO

1 file changed

+174
-85
lines changed

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX/TOOLCHAIN_ARM_MICRO/startup_LPC11xx.s

Lines changed: 174 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -1,59 +1,46 @@
1-
;/**************************************************************************//**
2-
; * @file startup_LPC11xx.s
3-
; * @brief CMSIS Cortex-M0 Core Device Startup File
4-
; * for the NXP LPC11xx/LPC11Cxx Device Series
5-
; * @version V1.10
6-
; * @date 24. November 2010
1+
;/*****************************************************************************
2+
; * @file: startup_LPC11xx.s
3+
; * @purpose: CMSIS Cortex-M0 Core Device Startup File
4+
; * for the NXP LPC11xx Device Series
5+
; * @version: V1.0
6+
; * @date: 25. Nov. 2008
77
; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
88
; *
9-
; * @note
10-
; * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
11-
; *
12-
; * @par
13-
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
9+
; * Copyright (C) 2008 ARM Limited. All rights reserved.
10+
; * ARM Limited (ARM) is supplying this software for use with Cortex-M0
1411
; * processor based microcontrollers. This file can be freely distributed
1512
; * within development tools that are supporting such ARM based processors.
1613
; *
17-
; * @par
1814
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
1915
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
2016
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
2117
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
2218
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
2319
; *
24-
; ******************************************************************************/
25-
26-
27-
; <h> Stack Configuration
28-
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
29-
; </h>
20+
; *****************************************************************************/
3021

31-
Stack_Size EQU 0x00000200
22+
Stack_Size EQU 0x00000400
3223

3324
AREA STACK, NOINIT, READWRITE, ALIGN=3
3425
EXPORT __initial_sp
35-
Stack_Mem SPACE Stack_Size
36-
__initial_sp EQU 0x10001000 ; Top of RAM from LPC1114
3726

27+
Stack_Mem SPACE Stack_Size
28+
__initial_sp EQU 0x10001000 ; Top of RAM from LPC1114
3829

39-
; <h> Heap Configuration
40-
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
41-
; </h>
4230

4331
Heap_Size EQU 0x00000000
4432

4533
AREA HEAP, NOINIT, READWRITE, ALIGN=3
4634
EXPORT __heap_base
4735
EXPORT __heap_limit
36+
4837
__heap_base
4938
Heap_Mem SPACE Heap_Size
5039
__heap_limit
5140

52-
5341
PRESERVE8
5442
THUMB
5543

56-
5744
; Vector Table Mapped to Address 0 at Reset
5845

5946
AREA RESET, DATA, READONLY
@@ -76,41 +63,129 @@ __Vectors DCD __initial_sp ; Top of Stack
7663
DCD PendSV_Handler ; PendSV Handler
7764
DCD SysTick_Handler ; SysTick Handler
7865

79-
; External Interrupts
80-
DCD WAKEUP_IRQHandler ; 16+ 0: Wakeup PIO0.0
81-
DCD WAKEUP_IRQHandler ; 16+ 1: Wakeup PIO0.1
82-
DCD WAKEUP_IRQHandler ; 16+ 2: Wakeup PIO0.2
83-
DCD WAKEUP_IRQHandler ; 16+ 3: Wakeup PIO0.3
84-
DCD WAKEUP_IRQHandler ; 16+ 4: Wakeup PIO0.4
85-
DCD WAKEUP_IRQHandler ; 16+ 5: Wakeup PIO0.5
86-
DCD WAKEUP_IRQHandler ; 16+ 6: Wakeup PIO0.6
87-
DCD WAKEUP_IRQHandler ; 16+ 7: Wakeup PIO0.7
88-
DCD WAKEUP_IRQHandler ; 16+ 8: Wakeup PIO0.8
89-
DCD WAKEUP_IRQHandler ; 16+ 9: Wakeup PIO0.9
90-
DCD WAKEUP_IRQHandler ; 16+10: Wakeup PIO0.10
91-
DCD WAKEUP_IRQHandler ; 16+11: Wakeup PIO0.11
92-
DCD WAKEUP_IRQHandler ; 16+12: Wakeup PIO1.0
93-
DCD CAN_IRQHandler ; 16+13: CAN
94-
DCD SSP1_IRQHandler ; 16+14: SSP1
95-
DCD I2C_IRQHandler ; 16+15: I2C
96-
DCD TIMER16_0_IRQHandler ; 16+16: 16-bit Counter-Timer 0
97-
DCD TIMER16_1_IRQHandler ; 16+17: 16-bit Counter-Timer 1
98-
DCD TIMER32_0_IRQHandler ; 16+18: 32-bit Counter-Timer 0
99-
DCD TIMER32_1_IRQHandler ; 16+19: 32-bit Counter-Timer 1
100-
DCD SSP0_IRQHandler ; 16+20: SSP0
101-
DCD UART_IRQHandler ; 16+21: UART
102-
DCD USB_IRQHandler ; 16+22: USB IRQ
103-
DCD USB_FIQHandler ; 16+24: USB FIQ
104-
DCD ADC_IRQHandler ; 16+24: A/D Converter
105-
DCD WDT_IRQHandler ; 16+25: Watchdog Timer
106-
DCD BOD_IRQHandler ; 16+26: Brown Out Detect
107-
DCD FMC_IRQHandler ; 16+27: IP2111 Flash Memory Controller
108-
DCD PIOINT3_IRQHandler ; 16+28: PIO INT3
109-
DCD PIOINT2_IRQHandler ; 16+29: PIO INT2
110-
DCD PIOINT1_IRQHandler ; 16+30: PIO INT1
111-
DCD PIOINT0_IRQHandler ; 16+31: PIO INT0
112-
113-
66+
DCD FLEX_INT0_IRQHandler ; All GPIO pin can be routed to FLEX_INTx
67+
DCD FLEX_INT1_IRQHandler ;
68+
DCD FLEX_INT2_IRQHandler ;
69+
DCD FLEX_INT3_IRQHandler ;
70+
DCD FLEX_INT4_IRQHandler ;
71+
DCD FLEX_INT5_IRQHandler ;
72+
DCD FLEX_INT6_IRQHandler ;
73+
DCD FLEX_INT7_IRQHandler ;
74+
DCD GINT0_IRQHandler ;
75+
DCD GINT1_IRQHandler ; PIO0 (0:7)
76+
DCD Reserved_IRQHandler ; Reserved
77+
DCD Reserved_IRQHandler ;
78+
DCD Reserved_IRQHandler ;
79+
DCD Reserved_IRQHandler ;
80+
DCD SSP1_IRQHandler ; SSP1
81+
DCD I2C_IRQHandler ; I2C
82+
DCD TIMER16_0_IRQHandler ; 16-bit Timer0
83+
DCD TIMER16_1_IRQHandler ; 16-bit Timer1
84+
DCD TIMER32_0_IRQHandler ; 32-bit Timer0
85+
DCD TIMER32_1_IRQHandler ; 32-bit Timer1
86+
DCD SSP0_IRQHandler ; SSP0
87+
DCD UART_IRQHandler ; UART
88+
DCD USB_IRQHandler ; USB IRQ
89+
DCD USB_FIQHandler ; USB FIQ
90+
DCD ADC_IRQHandler ; A/D Converter
91+
DCD WDT_IRQHandler ; Watchdog timer
92+
DCD BOD_IRQHandler ; Brown Out Detect
93+
DCD FMC_IRQHandler ; IP2111 Flash Memory Controller
94+
DCD Reserved_IRQHandler ; Reserved
95+
DCD Reserved_IRQHandler ; Reserved
96+
DCD Reserved_IRQHandler ; Reserved
97+
DCD Reserved_IRQHandler ; Reserved
98+
99+
;; 48 vector entries. We pad to 128 to fill the 0x0 - 0x1FF REMAP address space
100+
101+
DCD 0xFFFFFFFF ; Datafill
102+
DCD 0xFFFFFFFF ; Datafill
103+
DCD 0xFFFFFFFF ; Datafill
104+
DCD 0xFFFFFFFF ; Datafill
105+
DCD 0xFFFFFFFF ; Datafill
106+
DCD 0xFFFFFFFF ; Datafill
107+
DCD 0xFFFFFFFF ; Datafill
108+
DCD 0xFFFFFFFF ; Datafill
109+
DCD 0xFFFFFFFF ; Datafill
110+
DCD 0xFFFFFFFF ; Datafill
111+
112+
DCD 0xFFFFFFFF ; Datafill
113+
DCD 0xFFFFFFFF ; Datafill
114+
DCD 0xFFFFFFFF ; Datafill
115+
DCD 0xFFFFFFFF ; Datafill
116+
DCD 0xFFFFFFFF ; Datafill
117+
DCD 0xFFFFFFFF ; Datafill
118+
DCD 0xFFFFFFFF ; Datafill
119+
DCD 0xFFFFFFFF ; Datafill
120+
DCD 0xFFFFFFFF ; Datafill
121+
DCD 0xFFFFFFFF ; Datafill
122+
123+
DCD 0xFFFFFFFF ; Datafill
124+
DCD 0xFFFFFFFF ; Datafill
125+
DCD 0xFFFFFFFF ; Datafill
126+
DCD 0xFFFFFFFF ; Datafill
127+
DCD 0xFFFFFFFF ; Datafill
128+
DCD 0xFFFFFFFF ; Datafill
129+
DCD 0xFFFFFFFF ; Datafill
130+
DCD 0xFFFFFFFF ; Datafill
131+
DCD 0xFFFFFFFF ; Datafill
132+
DCD 0xFFFFFFFF ; Datafill
133+
134+
DCD 0xFFFFFFFF ; Datafill
135+
DCD 0xFFFFFFFF ; Datafill
136+
DCD 0xFFFFFFFF ; Datafill
137+
DCD 0xFFFFFFFF ; Datafill
138+
DCD 0xFFFFFFFF ; Datafill
139+
DCD 0xFFFFFFFF ; Datafill
140+
DCD 0xFFFFFFFF ; Datafill
141+
DCD 0xFFFFFFFF ; Datafill
142+
DCD 0xFFFFFFFF ; Datafill
143+
DCD 0xFFFFFFFF ; Datafill
144+
145+
DCD 0xFFFFFFFF ; Datafill
146+
DCD 0xFFFFFFFF ; Datafill
147+
DCD 0xFFFFFFFF ; Datafill
148+
DCD 0xFFFFFFFF ; Datafill
149+
DCD 0xFFFFFFFF ; Datafill
150+
DCD 0xFFFFFFFF ; Datafill
151+
DCD 0xFFFFFFFF ; Datafill
152+
DCD 0xFFFFFFFF ; Datafill
153+
DCD 0xFFFFFFFF ; Datafill
154+
DCD 0xFFFFFFFF ; Datafill
155+
156+
DCD 0xFFFFFFFF ; Datafill
157+
DCD 0xFFFFFFFF ; Datafill
158+
DCD 0xFFFFFFFF ; Datafill
159+
DCD 0xFFFFFFFF ; Datafill
160+
DCD 0xFFFFFFFF ; Datafill
161+
DCD 0xFFFFFFFF ; Datafill
162+
DCD 0xFFFFFFFF ; Datafill
163+
DCD 0xFFFFFFFF ; Datafill
164+
DCD 0xFFFFFFFF ; Datafill
165+
DCD 0xFFFFFFFF ; Datafill
166+
167+
DCD 0xFFFFFFFF ; Datafill
168+
DCD 0xFFFFFFFF ; Datafill
169+
DCD 0xFFFFFFFF ; Datafill
170+
DCD 0xFFFFFFFF ; Datafill
171+
DCD 0xFFFFFFFF ; Datafill
172+
DCD 0xFFFFFFFF ; Datafill
173+
DCD 0xFFFFFFFF ; Datafill
174+
DCD 0xFFFFFFFF ; Datafill
175+
DCD 0xFFFFFFFF ; Datafill
176+
DCD 0xFFFFFFFF ; Datafill
177+
178+
DCD 0xFFFFFFFF ; Datafill
179+
DCD 0xFFFFFFFF ; Datafill
180+
DCD 0xFFFFFFFF ; Datafill
181+
DCD 0xFFFFFFFF ; Datafill
182+
DCD 0xFFFFFFFF ; Datafill
183+
DCD 0xFFFFFFFF ; Datafill
184+
DCD 0xFFFFFFFF ; Datafill
185+
DCD 0xFFFFFFFF ; Datafill
186+
DCD 0xFFFFFFFF ; Datafill
187+
DCD 0xFFFFFFFF ; Datafill
188+
114189
IF :LNOT::DEF:NO_CRP
115190
AREA |.ARM.__at_0x02FC|, CODE, READONLY
116191
CRP_Key DCD 0xFFFFFFFF
@@ -120,6 +195,7 @@ CRP_Key DCD 0xFFFFFFFF
120195
AREA |.text|, CODE, READONLY
121196

122197

198+
123199
; Reset Handler
124200

125201
Reset_Handler PROC
@@ -132,13 +208,14 @@ Reset_Handler PROC
132208
BX R0
133209
ENDP
134210

135-
136211
; Dummy Exception Handlers (infinite loops which can be modified)
137212

138-
NMI_Handler PROC
139-
EXPORT NMI_Handler [WEAK]
140-
B .
141-
ENDP
213+
; now, under COMMON NMI.c and NMI.h, a real NMI handler is created if NMI is enabled
214+
; for particular peripheral.
215+
;NMI_Handler PROC
216+
; EXPORT NMI_Handler [WEAK]
217+
; B .
218+
; ENDP
142219
HardFault_Handler\
143220
PROC
144221
EXPORT HardFault_Handler [WEAK]
@@ -156,11 +233,24 @@ SysTick_Handler PROC
156233
EXPORT SysTick_Handler [WEAK]
157234
B .
158235
ENDP
236+
Reserved_IRQHandler PROC
237+
EXPORT Reserved_IRQHandler [WEAK]
238+
B .
239+
ENDP
159240

160241
Default_Handler PROC
161-
162-
EXPORT WAKEUP_IRQHandler [WEAK]
163-
EXPORT CAN_IRQHandler [WEAK]
242+
; for LPC11Uxx (With USB)
243+
EXPORT NMI_Handler [WEAK]
244+
EXPORT FLEX_INT0_IRQHandler [WEAK]
245+
EXPORT FLEX_INT1_IRQHandler [WEAK]
246+
EXPORT FLEX_INT2_IRQHandler [WEAK]
247+
EXPORT FLEX_INT3_IRQHandler [WEAK]
248+
EXPORT FLEX_INT4_IRQHandler [WEAK]
249+
EXPORT FLEX_INT5_IRQHandler [WEAK]
250+
EXPORT FLEX_INT6_IRQHandler [WEAK]
251+
EXPORT FLEX_INT7_IRQHandler [WEAK]
252+
EXPORT GINT0_IRQHandler [WEAK]
253+
EXPORT GINT1_IRQHandler [WEAK]
164254
EXPORT SSP1_IRQHandler [WEAK]
165255
EXPORT I2C_IRQHandler [WEAK]
166256
EXPORT TIMER16_0_IRQHandler [WEAK]
@@ -169,19 +259,26 @@ Default_Handler PROC
169259
EXPORT TIMER32_1_IRQHandler [WEAK]
170260
EXPORT SSP0_IRQHandler [WEAK]
171261
EXPORT UART_IRQHandler [WEAK]
262+
172263
EXPORT USB_IRQHandler [WEAK]
173264
EXPORT USB_FIQHandler [WEAK]
174265
EXPORT ADC_IRQHandler [WEAK]
175266
EXPORT WDT_IRQHandler [WEAK]
176267
EXPORT BOD_IRQHandler [WEAK]
177268
EXPORT FMC_IRQHandler [WEAK]
178-
EXPORT PIOINT3_IRQHandler [WEAK]
179-
EXPORT PIOINT2_IRQHandler [WEAK]
180-
EXPORT PIOINT1_IRQHandler [WEAK]
181-
EXPORT PIOINT0_IRQHandler [WEAK]
182-
183-
WAKEUP_IRQHandler
184-
CAN_IRQHandler
269+
EXPORT USBWakeup_IRQHandler [WEAK]
270+
271+
NMI_Handler
272+
FLEX_INT0_IRQHandler
273+
FLEX_INT1_IRQHandler
274+
FLEX_INT2_IRQHandler
275+
FLEX_INT3_IRQHandler
276+
FLEX_INT4_IRQHandler
277+
FLEX_INT5_IRQHandler
278+
FLEX_INT6_IRQHandler
279+
FLEX_INT7_IRQHandler
280+
GINT0_IRQHandler
281+
GINT1_IRQHandler
185282
SSP1_IRQHandler
186283
I2C_IRQHandler
187284
TIMER16_0_IRQHandler
@@ -196,19 +293,11 @@ ADC_IRQHandler
196293
WDT_IRQHandler
197294
BOD_IRQHandler
198295
FMC_IRQHandler
199-
PIOINT3_IRQHandler
200-
PIOINT2_IRQHandler
201-
PIOINT1_IRQHandler
202-
PIOINT0_IRQHandler
296+
USBWakeup_IRQHandler
203297

204298
B .
205299

206300
ENDP
207301

208302
ALIGN
209-
210-
; @toyowata removed "User Initial Stack & Heap" block here,
211-
; since arm.py script doesn't pass -D__MICROLIB definision to armasm.
212-
; Now, required symbols (__initial_sp etc) were exported in this code.
213-
214303
END

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