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32 | 32 | #define __CTHUNK_H__
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33 | 33 |
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34 | 34 | #define CTHUNK_ADDRESS 1
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| 35 | +#define CTHUNK_VARIABLES volatile uint32_t code[2] |
35 | 36 |
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36 |
| -#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)) && ! defined(__CORTEX_A9) |
37 |
| -#define CTHUNK_VARIABLES volatile uint32_t code[1] |
| 37 | +#if (defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__CORTEX_M7) || defined(__CORTEX_A9)) |
38 | 38 | /**
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39 |
| -* CTHUNK disassembly for Cortex-M3/M4 (thumb2): |
40 |
| -* * ldm.w pc,{r0,r1,r2,pc} |
| 39 | +* CTHUNK disassembly for Cortex-M3/M4/M7/A9 (thumb2): |
| 40 | +* * adr r0, #4 |
| 41 | +* * ldm r0, {r0, r1, r2, pc} |
41 | 42 | *
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42 | 43 | * This instruction loads the arguments for the static thunking function to r0-r2, and
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43 | 44 | * branches to that function by loading its address into PC.
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44 | 45 | *
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45 | 46 | * This is safe for both regular calling and interrupt calling, since it only touches scratch registers
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46 | 47 | * which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
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47 | 48 | */
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48 |
| -#define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F |
| 49 | +#define CTHUNK_ASSIGMENT do { \ |
| 50 | + m_thunk.code[0] = 0xE890A001; \ |
| 51 | + m_thunk.code[1] = 0x00008007; \ |
| 52 | + } while (0) |
49 | 53 |
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50 |
| -#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0) || defined(__CORTEX_A9) |
| 54 | +#elif (defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0)) |
51 | 55 | /*
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52 |
| -* CTHUNK disassembly for Cortex M0 (thumb): |
53 |
| -* * push {r0,r1,r2,r3,r4,lr} save touched registers and return address |
54 |
| -* * movs r4,#4 set up address to load arguments from (immediately following this code block) (1) |
55 |
| -* * add r4,pc set up address to load arguments from (immediately following this code block) (2) |
56 |
| -* * ldm r4!,{r0,r1,r2,r3} load arguments for static thunk function |
57 |
| -* * blx r3 call static thunk function |
58 |
| -* * pop {r0,r1,r2,r3,r4,pc} restore scratch registers and return from function |
| 56 | +* CTHUNK disassembly for Cortex M0/M0+ (thumb): |
| 57 | +* * adr r0, #4 |
| 58 | +* * ldm r0, {r0, r1, r2, r3} |
| 59 | +* * bx r3 |
59 | 60 | */
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60 |
| -#define CTHUNK_VARIABLES volatile uint32_t code[3] |
61 | 61 | #define CTHUNK_ASSIGMENT do { \
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62 |
| - m_thunk.code[0] = 0x2404B51F; \ |
63 |
| - m_thunk.code[1] = 0xCC0F447C; \ |
64 |
| - m_thunk.code[2] = 0xBD1F4798; \ |
| 62 | + m_thunk.code[0] = 0xC80FA001; \ |
| 63 | + m_thunk.code[1] = 0x00004718; \ |
65 | 64 | } while (0)
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66 | 65 |
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67 | 66 | #else
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@@ -225,6 +224,13 @@ class CThunk
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225 | 224 | __ca9u_inv_tlb_all();
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226 | 225 | __v7_inv_btac();
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227 | 226 | }
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| 227 | +#endif |
| 228 | +#if defined(__CORTEX_M7) |
| 229 | + /* Data cache clean and invalid */ |
| 230 | + SCB_CleanInvalidateDCache(); |
| 231 | + |
| 232 | + /* Instruction cache invalid */ |
| 233 | + SCB_InvalidateICache(); |
228 | 234 | #endif
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229 | 235 | __ISB();
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230 | 236 | __DSB();
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