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Merge pull request #806 from bcostm/master
Targets: NUCLEO_F0 - Align registers and system files with latest CMSIS files
2 parents bd803e5 + 4dd46fd commit b170bc7

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12 files changed

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‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h

Lines changed: 19 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32f030x8.h
44
* @author MCD Application Team
5-
* @version V2.1.0
6-
* @date 03-Oct-2014
5+
* @version V2.2.0
6+
* @date 05-December-2014
77
* @brief CMSIS STM32F030x8 devices Peripheral Access Layer Header File.
88
*
99
* This file contains:
@@ -371,24 +371,15 @@ typedef struct
371371

372372
typedef struct
373373
{
374-
__IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
375-
uint16_t RESERVED0; /*!< Reserved, 0x02 */
376-
__IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
377-
uint16_t RESERVED1; /*!< Reserved, 0x06 */
378-
__IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
379-
uint16_t RESERVED2; /*!< Reserved, 0x0A */
380-
__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
381-
uint16_t RESERVED3; /*!< Reserved, 0x0E */
382-
__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
383-
uint16_t RESERVED4; /*!< Reserved, 0x12 */
384-
__IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
385-
uint16_t RESERVED5; /*!< Reserved, 0x16 */
386-
__IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
387-
uint16_t RESERVED6; /*!< Reserved, 0x1A */
388-
__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
389-
uint16_t RESERVED7; /*!< Reserved, 0x1E */
390-
__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
391-
uint16_t RESERVED8; /*!< Reserved, 0x22 */
374+
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
375+
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
376+
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
377+
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
378+
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
379+
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
380+
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
381+
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
382+
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
392383
}SPI_TypeDef;
393384

394385
/**
@@ -2951,13 +2942,15 @@ typedef struct
29512942
((INSTANCE) == DMA1_Channel5))
29522943

29532944
/****************************** GPIO Instances ********************************/
2954-
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
2955-
((INSTANCE) == GPIOB) || \
2956-
((INSTANCE) == GPIOC) || \
2957-
((INSTANCE) == GPIOD) || \
2958-
((INSTANCE) == GPIOF))
2945+
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
2946+
((INSTANCE) == GPIOB) || \
2947+
((INSTANCE) == GPIOC) || \
2948+
((INSTANCE) == GPIOD) || \
2949+
((INSTANCE) == GPIOF))
2950+
2951+
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
2952+
((INSTANCE) == GPIOB))
29592953

2960-
/****************************** GPIO Lock Instances ****************************/
29612954
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
29622955
((INSTANCE) == GPIOB))
29632956

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f0xx.h

Lines changed: 17 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32f0xx.h
44
* @author MCD Application Team
5-
* @version V2.1.0
6-
* @date 03-Oct-2014
5+
* @version V2.2.0
6+
* @date 05-December-2014
77
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
88
*
99
* The file is the unique include file that the application programmer
@@ -70,10 +70,10 @@
7070

7171
#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
7272
!defined (STM32F031x6) && !defined (STM32F038xx) && \
73-
!defined (STM32F042x6) && !defined (STM32F048xx) && \
73+
!defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
7474
!defined (STM32F051x8) && !defined (STM32F058xx) && \
75-
!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && \
76-
!defined (STM32F091xC) && !defined (STM32F098xx)
75+
!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
76+
!defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
7777
/* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
7878
#define STM32F030x8 /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
7979
/* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
@@ -82,9 +82,12 @@
8282
/* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
8383
/* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
8484
/* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
85+
/* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
86+
/* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
8587
/* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
8688
/* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
8789
/* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
90+
/* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
8891
/* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
8992
/* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
9093
#endif
@@ -102,10 +105,10 @@
102105
#endif /* USE_HAL_DRIVER */
103106

104107
/**
105-
* @brief CMSIS Device version number V2.1.0
108+
* @brief CMSIS Device version number V2.2.0
106109
*/
107110
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
108-
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
111+
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
109112
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
110113
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
111114
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
@@ -137,6 +140,10 @@
137140
#include "stm32f051x8.h"
138141
#elif defined(STM32F058xx)
139142
#include "stm32f058xx.h"
143+
#elif defined(STM32F070x6)
144+
#include "stm32f070x6.h"
145+
#elif defined(STM32F070xB)
146+
#include "stm32f070xb.h"
140147
#elif defined(STM32F071xB)
141148
#include "stm32f071xb.h"
142149
#elif defined(STM32F072xB)
@@ -146,7 +153,9 @@
146153
#elif defined(STM32F091xC)
147154
#include "stm32f091xc.h"
148155
#elif defined(STM32F098xx)
149-
#include "stm32f098xx.h"
156+
#include "stm32f098xx.h"
157+
#elif defined(STM32F030xC)
158+
#include "stm32f030xc.h"
150159
#else
151160
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
152161
#endif

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c

Lines changed: 31 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file system_stm32f0xx.c
44
* @author MCD Application Team
5-
* @version V2.1.0
6-
* @date 03-Oct-2014
5+
* @version V2.2.0
6+
* @date 05-December-2014
77
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
88
*
99
* 1. This file provides two functions and one global variable to be called from
@@ -135,6 +135,7 @@
135135
updated automatically.
136136
*/
137137
uint32_t SystemCoreClock = 48000000;
138+
138139
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
139140

140141
/**
@@ -191,15 +192,31 @@ void SystemInit(void)
191192
/* Reset PREDIV[3:0] bits */
192193
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
193194

194-
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
195-
/* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
195+
#if defined (STM32F072xB) || defined (STM32F078xB)
196+
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
196197
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
198+
#elif defined (STM32F071xB)
199+
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
200+
RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
197201
#elif defined (STM32F091xC) || defined (STM32F098xx)
198-
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
199-
RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
200-
#else
201-
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
202+
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
203+
RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
204+
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
205+
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
206+
RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
207+
#elif defined (STM32F051x8) || defined (STM32F058xx)
208+
/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
209+
RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
210+
#elif defined (STM32F042x6) || defined (STM32F048xx)
211+
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
202212
RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
213+
#elif defined (STM32F070x6) || defined (STM32F070xB)
214+
/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
215+
RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
216+
/* Set default USB clock to PLLCLK, since there is no HSI48 */
217+
RCC->CFGR3 |= (uint32_t)0x00000080;
218+
#else
219+
#warning "No target selected"
203220
#endif
204221

205222
/* Reset HSI14 bit */
@@ -288,13 +305,17 @@ void SystemCoreClockUpdate (void)
288305
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
289306
else
290307
{
291-
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
308+
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
309+
defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
310+
defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
292311
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
293312
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
294313
#else
295314
/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
296315
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
297-
#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
316+
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
317+
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
318+
STM32F091xC || STM32F098xx || STM32F030xC */
298319
}
299320
break;
300321
default: /* HSI used as system clock */

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file system_stm32f0xx.h
44
* @author MCD Application Team
5-
* @version V2.1.0
6-
* @date 03-Oct-2014
5+
* @version V2.2.0
6+
* @date 05-December-2014
77
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
88
******************************************************************************
99
* @attention

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h

Lines changed: 24 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
******************************************************************************
33
* @file stm32f072xb.h
44
* @author MCD Application Team
5-
* @version V2.1.0
6-
* @date 03-Oct-2014
5+
* @version V2.2.0
6+
* @date 05-December-2014
77
* @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
88
*
99
* This file contains:
@@ -506,24 +506,15 @@ typedef struct
506506

507507
typedef struct
508508
{
509-
__IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
510-
uint16_t RESERVED0; /*!< Reserved, 0x02 */
511-
__IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
512-
uint16_t RESERVED1; /*!< Reserved, 0x06 */
513-
__IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
514-
uint16_t RESERVED2; /*!< Reserved, 0x0A */
515-
__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
516-
uint16_t RESERVED3; /*!< Reserved, 0x0E */
517-
__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
518-
uint16_t RESERVED4; /*!< Reserved, 0x12 */
519-
__IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
520-
uint16_t RESERVED5; /*!< Reserved, 0x16 */
521-
__IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
522-
uint16_t RESERVED6; /*!< Reserved, 0x1A */
523-
__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
524-
uint16_t RESERVED7; /*!< Reserved, 0x1E */
525-
__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
526-
uint16_t RESERVED8; /*!< Reserved, 0x22 */
509+
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
510+
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
511+
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
512+
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
513+
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
514+
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
515+
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
516+
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
517+
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
527518
}SPI_TypeDef;
528519

529520
/**
@@ -5237,14 +5228,19 @@ typedef struct
52375228
((INSTANCE) == DMA1_Channel7))
52385229

52395230
/****************************** GPIO Instances ********************************/
5240-
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5241-
((INSTANCE) == GPIOB) || \
5242-
((INSTANCE) == GPIOC) || \
5243-
((INSTANCE) == GPIOD) || \
5244-
((INSTANCE) == GPIOE) || \
5245-
((INSTANCE) == GPIOF))
5246-
5247-
/****************************** GPIO Lock Instances ****************************/
5231+
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5232+
((INSTANCE) == GPIOB) || \
5233+
((INSTANCE) == GPIOC) || \
5234+
((INSTANCE) == GPIOD) || \
5235+
((INSTANCE) == GPIOE) || \
5236+
((INSTANCE) == GPIOF))
5237+
5238+
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
5239+
((INSTANCE) == GPIOB) || \
5240+
((INSTANCE) == GPIOC) || \
5241+
((INSTANCE) == GPIOD) || \
5242+
((INSTANCE) == GPIOE))
5243+
52485244
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
52495245
((INSTANCE) == GPIOB))
52505246

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