Fix: reverted unwanted changes in ARM5's scatter files of legacy nRF51822 targets.

nvlsianpu · nvlsianpu · commit b49f85fe462f · 2016-10-10T09:45:31.000+02:00
Applied proper changes to ARM5's scatter files of nRF5 regular targets.
Improvement: Remove hardcoding of FLASH vector address, now FLASH vector address is imported form linker to C code.


Signed-off-by: Andrzej Puzdrowski &lt;andrzej.puzdrowski@nordicsemi.no&gt;
diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
@@ -18,10 +18,7 @@ LR_IROM1 0x1C000 0x0024000  {
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM0 0x20002800 UNINIT 0x000000c0  { ;no init section
-        *(noinit)
-  }
-  RW_IRAM1 0x200028C0 0x00005740  {
+  RW_IRAM1 0x20002800 0x00005800  {
    .ANY (+RW +ZI)
   }
 }
diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
@@ -18,10 +18,7 @@ LR_IROM1 0x18000 0x0028000  {
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM0 0x20002000 UNINIT 0x000000c0  { ;no init section
-        *(noinit)
-  }
-  RW_IRAM1 0x200020C0 0x00001F40  {
+  RW_IRAM1 0x20002000 0x00002000  {
    .ANY (+RW +ZI)
   }
 }
diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
@@ -18,10 +18,7 @@ LR_IROM1 0x1C000 0x0024000  {
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM0 0x20002800 UNINIT 0x000000c0  { ;no init section
-        *(noinit)
-  }
-  RW_IRAM1 0x200028C0 0x00001740  {
+  RW_IRAM1 0x20002800 0x00001800  {
    .ANY (+RW +ZI)
   }
 }
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
@@ -12,13 +12,16 @@
 ;
 ;WITH SOFTDEVICE:
 
-LR_IROM1 0x0001B000 0x0025000  {
-  ER_IROM1 0x0001B000 0x0025000  {
+LR_IROM1 0x1B000 0x0025000  {
+  ER_IROM1 0x1B000 0x0025000  {
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20002ef8 0x5108  {
+  RW_IRAM0 0x20002ef8 UNINIT 0x000000c0  { ;no init section
+        *(noinit)
+  }
+  RW_IRAM1 0x20002FB8 0x00005048  {
    .ANY (+RW +ZI)
   }
 }
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
@@ -12,13 +12,16 @@
 ;
 ;WITH SOFTDEVICE:
 
-LR_IROM1 0x0001B000 0x0025000  {
-  ER_IROM1 0x0001B000 0x0025000  {
+LR_IROM1 0x18000 0x0028000  {
+  ER_IROM1 0x18000 0x0028000  {
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20002ef8 0x1108  {
+  RW_IRAM0 0x20002000 UNINIT 0x000000c0  { ;no init section
+        *(noinit)
+  }
+  RW_IRAM1 0x200020C0 0x00001F40  {
    .ANY (+RW +ZI)
   }
 }
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
@@ -18,7 +18,10 @@ LR_IROM1 0x0001B000 0x0025000  {
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  RW_IRAM1 0x20002ef8 0x1108  {
+  RW_IRAM0 0x20002ef8 UNINIT 0x000000c0  { ;no init section
+        *(noinit)
+  }
+  RW_IRAM1 0x20002FB8 0x00001048  {
    .ANY (+RW +ZI)
   }
 }
diff --git a/targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c b/targets/TARGET_NORDIC/TARGET_NRF5/reloc_vector_table.c
@@ -56,13 +56,8 @@
 typedef void (*generic_irq_handler_t)(void);
 
 
-#ifdef NRF52
-#define VECTORS_FLASH_START 0x1C000
-#endif
-
-#ifdef NRF51
-#define VECTORS_FLASH_START 0x1B000
-#endif
+extern uint32_t __Vectors[];
+#define VECTORS_FLASH_START __Vectors
 
 /**
  * @brief Function for relocation of the vector to RAM on nRF5x devices.

Original file line number	Diff line number	Diff line change
`@@ -18,10 +18,7 @@ LR_IROM1 0x1C000 0x0024000 {`
`18`	`18`	`*(InRoot$$Sections)`
`19`	`19`	`.ANY (+RO)`
`20`	`20`	`}`
`21`		`- RW_IRAM0 0x20002800 UNINIT 0x000000c0 { ;no init section`
`22`		`- *(noinit)`
`23`		`- }`
`24`		`- RW_IRAM1 0x200028C0 0x00005740 {`
	`21`	`+ RW_IRAM1 0x20002800 0x00005800 {`
`25`	`22`	`.ANY (+RW +ZI)`
`26`	`23`	`}`
`27`	`24`	`}`
Original file line number	Diff line number	Diff line change
`@@ -18,10 +18,7 @@ LR_IROM1 0x18000 0x0028000 {`
`18`	`18`	`*(InRoot$$Sections)`
`19`	`19`	`.ANY (+RO)`
`20`	`20`	`}`
`21`		`- RW_IRAM0 0x20002000 UNINIT 0x000000c0 { ;no init section`
`22`		`- *(noinit)`
`23`		`- }`
`24`		`- RW_IRAM1 0x200020C0 0x00001F40 {`
	`21`	`+ RW_IRAM1 0x20002000 0x00002000 {`
`25`	`22`	`.ANY (+RW +ZI)`
`26`	`23`	`}`
`27`	`24`	`}`
Original file line number	Diff line number	Diff line change
`@@ -12,13 +12,16 @@`
`12`	`12`	`;`
`13`	`13`	`;WITH SOFTDEVICE:`
`14`	`14`
`15`		`-LR_IROM1 0x0001B000 0x0025000 {`
`16`		`- ER_IROM1 0x0001B000 0x0025000 {`
	`15`	`+LR_IROM1 0x1B000 0x0025000 {`
	`16`	`+ ER_IROM1 0x1B000 0x0025000 {`
`17`	`17`	`*.o (RESET, +First)`
`18`	`18`	`*(InRoot$$Sections)`
`19`	`19`	`.ANY (+RO)`
`20`	`20`	`}`
`21`		`- RW_IRAM1 0x20002ef8 0x5108 {`
	`21`	`+ RW_IRAM0 0x20002ef8 UNINIT 0x000000c0 { ;no init section`
	`22`	`+ *(noinit)`
	`23`	`+ }`
	`24`	`+ RW_IRAM1 0x20002FB8 0x00005048 {`
`22`	`25`	`.ANY (+RW +ZI)`
`23`	`26`	`}`
`24`	`27`	`}`
Original file line number	Diff line number	Diff line change
`@@ -18,7 +18,10 @@ LR_IROM1 0x0001B000 0x0025000 {`
`18`	`18`	`*(InRoot$$Sections)`
`19`	`19`	`.ANY (+RO)`
`20`	`20`	`}`
`21`		`- RW_IRAM1 0x20002ef8 0x1108 {`
	`21`	`+ RW_IRAM0 0x20002ef8 UNINIT 0x000000c0 { ;no init section`
	`22`	`+ *(noinit)`
	`23`	`+ }`
	`24`	`+ RW_IRAM1 0x20002FB8 0x00001048 {`
`22`	`25`	`.ANY (+RW +ZI)`
`23`	`26`	`}`
`24`	`27`	`}`