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VladimirUmekTomoYamanaka
VladimirUmek
authored and
TomoYamanaka
committed
RTX5: ignoring CPUID field in GIC implementation
 updated interrupt handler for GCC and IAR
1 parent 0226b11 commit b6c4139

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3 files changed

+46
-14
lines changed

3 files changed

+46
-14
lines changed

‎cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file irq_ctrl_gic.c
33
* @brief Interrupt controller handling implementation for GIC
4-
* @version V1.0.0
5-
* @date 30. June 2017
4+
* @version V1.0.1
5+
* @date 9. April 2018
66
******************************************************************************/
77
/*
88
* Copyright (c) 2017 ARM Limited. All rights reserved.
@@ -37,7 +37,7 @@
3737
#endif
3838

3939
static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
40-
static uint32_t IRQ_ID0;
40+
static uint32_t IRQ_ID0;
4141

4242
/// Initialize interrupt controller.
4343
__WEAK int32_t IRQ_Initialize (void) {
@@ -70,6 +70,9 @@ __WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
7070
__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
7171
IRQHandler_t h;
7272

73+
// Ignore CPUID field (software generated interrupts)
74+
irqn &= 0x3FFU;
75+
7376
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
7477
h = IRQTable[irqn];
7578
} else {
@@ -271,9 +274,12 @@ __WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
271274
/// Signal end of interrupt processing.
272275
__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
273276
int32_t status;
277+
IRQn_Type irq = (IRQn_Type)irqn;
278+
279+
irqn &= 0x3FFU;
274280

275281
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
276-
GIC_EndInterrupt ((IRQn_Type)irqn);
282+
GIC_EndInterrupt (irq);
277283

278284
if (irqn == 0) {
279285
IRQ_ID0 = 0U;

‎rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_GCC/TARGET_CORTEX_A/irq_ca.S

Lines changed: 18 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -218,22 +218,35 @@ IRQ_End:
218218
LDR R0, =SVC_Active
219219
LDRB R0, [R0] // Load SVC_Active flag
220220
CMP R0, #0
221-
BNE IRQ_SwitchCheck // Skip post processing when SVC active
221+
BNE IRQ_Exit // SVC active, exit from IRQ handler
222222

223223
// RTX IRQ post processing check
224+
LDR R4, =IRQ_PendSV // Load address of IRQ_PendSV flag
225+
LDRB R0, [R4] // Load PendSV flag
226+
CMP R0, #1 // Compare PendSV value
227+
BNE IRQ_SwitchCheck // Skip post processing if not pending
228+
224229
PUSH {R5, R6} // Save user R5 and R6
225-
MOV R6, #0
226-
LDR R5, =IRQ_PendSV // Load address of IRQ_PendSV flag
230+
// Disable OS Tick
231+
LDR R5, =osRtxInfo // Load address of osRtxInfo
232+
LDR R5, [R5, #I_TICK_IRQN_OFS] // Load OS Tick irqn
233+
MOV R0, R5 // Set it as function parameter
234+
BLX IRQ_Disable // Disable OS Tick interrupt
235+
MOV R6, #0 // Set PendSV clear value
227236
B IRQ_PendCheck
228237
IRQ_PendExec:
229-
STRB R6, [R5] // Clear PendSV flag
238+
STRB R6, [R4] // Clear PendSV flag
230239
CPSIE i // Re-enable interrupts
231240
BLX osRtxPendSV_Handler // Post process pending objects
232241
CPSID i // Disable interrupts
233242
IRQ_PendCheck:
234-
LDRB R0, [R5] // Load PendSV flag
243+
LDRB R0, [R4] // Load PendSV flag
235244
CMP R0, #1 // Compare PendSV value
236245
BEQ IRQ_PendExec // Branch to IRQ_PendExec if PendSV is set
246+
247+
// Re-enable OS Tick
248+
MOV R0, R5 // Restore irqn as function parameter
249+
BLX IRQ_Enable // Enable OS Tick interrupt
237250
POP {R5, R6} // Restore user R5 and R6
238251

239252
IRQ_SwitchCheck:

‎rtos/TARGET_CORTEX/rtx5/RTX/Source/TOOLCHAIN_IAR/TARGET_CORTEX_A/irq_ca.S

Lines changed: 18 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -203,22 +203,35 @@ IRQ_End
203203
LDR R0, =SVC_Active
204204
LDRB R0, [R0] ; Load SVC_Active flag
205205
CMP R0, #0
206-
BNE IRQ_SwitchCheck ; Skip post processing when SVC active
206+
BNE IRQ_Exit ; SVC active, exit from IRQ handler
207207

208208
; RTX IRQ post processing check
209+
LDR R4, =IRQ_PendSV ; Load address of IRQ_PendSV flag
210+
LDRB R0, [R4] ; Load PendSV flag
211+
CMP R0, #1 ; Compare PendSV value
212+
BNE IRQ_SwitchCheck ; Skip post processing if not pending
213+
209214
PUSH {R5, R6} ; Save user R5 and R6
210-
MOV R6, #0
211-
LDR R5, =IRQ_PendSV ; Load address of IRQ_PendSV flag
215+
; Disable OS Tick
216+
LDR R5, =osRtxInfo ; Load address of osRtxInfo
217+
LDR R5, [R5, #I_TICK_IRQN_OFS] ; Load OS Tick irqn
218+
MOV R0, R5 ; Set it as function parameter
219+
BLX IRQ_Disable ; Disable OS Tick interrupt
220+
MOV R6, #0 ; Set PendSV clear value
212221
B IRQ_PendCheck
213222
IRQ_PendExec
214-
STRB R6, [R5] ; Clear PendSV flag
223+
STRB R6, [R4] ; Clear PendSV flag
215224
CPSIE i ; Re-enable interrupts
216225
BLX osRtxPendSV_Handler ; Post process pending objects
217226
CPSID i ; Disable interrupts
218227
IRQ_PendCheck
219-
LDRB R0, [R5] ; Load PendSV flag
228+
LDRB R0, [R4] ; Load PendSV flag
220229
CMP R0, #1 ; Compare PendSV value
221230
BEQ IRQ_PendExec ; Branch to IRQ_PendExec if PendSV is set
231+
232+
; Re-enable OS Tick
233+
MOV R0, R5 ; Restore irqn as function parameter
234+
BLX IRQ_Enable ; Enable OS Tick interrupt
222235
POP {R5, R6} ; Restore user R5 and R6
223236

224237
IRQ_SwitchCheck

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