|
36 | 36 | extern "C" {
|
37 | 37 | #endif
|
38 | 38 |
|
39 |
| -#define STM_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((MODE & 0x0F) << 0) |\ |
40 |
| - ((PUPD & 0x07) << 4) |\ |
41 |
| - ((AFNUM & 0x0F) << 7))) |
42 |
| - |
43 |
| -#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED) ((int)(((MODE & 0x0F) << 0) |\ |
44 |
| - ((PUPD & 0x07) << 4) |\ |
45 |
| - ((AFNUM & 0x0F) << 7) |\ |
46 |
| - ((CHANNEL & 0x1F) << 11) |\ |
47 |
| - ((INVERTED & 0x01) << 16))) |
48 |
| - |
49 |
| -#define STM_PIN_MODE(X) (((X) >> 0) & 0x0F) |
50 |
| -#define STM_PIN_PUPD(X) (((X) >> 4) & 0x07) |
51 |
| -#define STM_PIN_AFNUM(X) (((X) >> 7) & 0x0F) |
52 |
| -#define STM_PIN_CHANNEL(X) (((X) >> 11) & 0x1F) |
53 |
| -#define STM_PIN_INVERTED(X) (((X) >> 16) & 0x01) |
54 |
| - |
55 |
| -#define STM_MODE_INPUT (0) |
56 |
| -#define STM_MODE_OUTPUT_PP (1) |
57 |
| -#define STM_MODE_OUTPUT_OD (2) |
58 |
| -#define STM_MODE_AF_PP (3) |
59 |
| -#define STM_MODE_AF_OD (4) |
60 |
| -#define STM_MODE_ANALOG (5) |
61 |
| -#define STM_MODE_IT_RISING (6) |
62 |
| -#define STM_MODE_IT_FALLING (7) |
63 |
| -#define STM_MODE_IT_RISING_FALLING (8) |
64 |
| -#define STM_MODE_EVT_RISING (9) |
65 |
| -#define STM_MODE_EVT_FALLING (10) |
66 |
| -#define STM_MODE_EVT_RISING_FALLING (11) |
67 |
| -#define STM_MODE_IT_EVT_RESET (12) |
68 |
| -// The last mode is only valid for specific families, so we put it in the end |
69 |
| -#define STM_MODE_ANALOG_ADC_CONTROL (13) |
| 39 | +/* STM PIN data as used in pin_function is coded on 32 bits as below |
| 40 | + * [2:0] Function (like in MODER reg) : Input / Output / Alt / Analog |
| 41 | + * [3] Output Push-Pull / Open Drain (as in OTYPER reg) |
| 42 | + * [5:4] as in PUPDR reg: No Pull, Pull-up, Pull-Donc |
| 43 | + * [7:6] Reserved for speed config (as in OSPEEDR), but not used yet |
| 44 | + * [11:8] Alternate Num (as in AFRL/AFRG reg) |
| 45 | + * [16:12] Channel (Analog/Timer specific) |
| 46 | + * [17] Inverted (Analog/Timer specific) |
| 47 | + * [18] Analog ADC control - Only valid for specific families |
| 48 | + * [32:19] Reserved |
| 49 | + */ |
| 50 | + |
| 51 | +#define STM_PIN_FUNCTION_MASK 0x07 |
| 52 | +#define STM_PIN_FUNCTION_SHIFT 0 |
| 53 | +#define STM_PIN_FUNCTION_BITS (STM_PIN_FUNCTION_MASK << STM_PIN_FUNCTION_SHIFT) |
| 54 | + |
| 55 | +#define STM_PIN_OD_MASK 0x01 |
| 56 | +#define STM_PIN_OD_SHIFT 3 |
| 57 | +#define STM_PIN_OD_BITS (STM_PIN_OD_MASK << STM_PIN_OD_SHIFT) |
| 58 | + |
| 59 | +#define STM_PIN_PUPD_MASK 0x03 |
| 60 | +#define STM_PIN_PUPD_SHIFT 4 |
| 61 | +#define STM_PIN_PUPD_BITS (STM_PIN_PUPD_MASK << STM_PIN_PUPD_SHIFT) |
| 62 | + |
| 63 | +#define STM_PIN_SPEED_MASK 0x03 |
| 64 | +#define STM_PIN_SPEED_SHIFT 6 |
| 65 | +#define STM_PIN_SPEED_BITS (STM_PIN_SPEED_MASK << STM_PIN_SPEED_SHIFT) |
| 66 | + |
| 67 | +#define STM_PIN_AFNUM_MASK 0x0F |
| 68 | +#define STM_PIN_AFNUM_SHIFT 8 |
| 69 | +#define STM_PIN_AFNUM_BITS (STM_PIN_AFNUM_MASK << STM_PIN_AFNUM_SHIFT) |
| 70 | + |
| 71 | +#define STM_PIN_CHAN_MASK 0x1F |
| 72 | +#define STM_PIN_CHAN_SHIFT 12 |
| 73 | +#define STM_PIN_CHANNEL_BIT (STM_PIN_CHAN_MASK << STM_PIN_CHAN_SHIFT) |
| 74 | + |
| 75 | +#define STM_PIN_INV_MASK 0x01 |
| 76 | +#define STM_PIN_INV_SHIFT 17 |
| 77 | +#define STM_PIN_INV_BIT (STM_PIN_INV_MASK << STM_PIN_INV_SHIFT) |
| 78 | + |
| 79 | +#define STM_PIN_AN_CTRL_MASK 0x01 |
| 80 | +#define STM_PIN_AN_CTRL_SHIFT 18 |
| 81 | +#define STM_PIN_ANALOG_CONTROL_BIT (STM_PIN_AN_CTRL_MASK << STM_PIN_AN_CTRL_SHIFT) |
| 82 | + |
| 83 | +#define STM_PIN_FUNCTION(X) (((X) >> STM_PIN_FUNCTION_SHIFT) & STM_PIN_FUNCTION_MASK) |
| 84 | +#define STM_PIN_OD(X) (((X) >> STM_PIN_OD_SHIFT) & STM_PIN_OD_MASK) |
| 85 | +#define STM_PIN_PUPD(X) (((X) >> STM_PIN_PUPD_SHIFT) & STM_PIN_PUPD_MASK) |
| 86 | +#define STM_PIN_SPEED(X) (((X) >> STM_PIN_SPEED_SHIFT) & STM_PIN_SPEED_MASK) |
| 87 | +#define STM_PIN_AFNUM(X) (((X) >> STM_PIN_AFNUM_SHIFT) & STM_PIN_AFNUM_MASK) |
| 88 | +#define STM_PIN_CHANNEL(X) (((X) >> STM_PIN_CHAN_SHIFT) & STM_PIN_CHAN_MASK) |
| 89 | +#define STM_PIN_INVERTED(X) (((X) >> STM_PIN_INV_SHIFT) & STM_PIN_INV_MASK) |
| 90 | +#define STM_PIN_ANALOG_CONTROL(X) (((X) >> STM_PIN_AN_CTRL_SHIFT) & STM_PIN_AN_CTRL_MASK) |
| 91 | + |
| 92 | +#define STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM) ((int)(FUNC_OD) |\ |
| 93 | + ((PUPD & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ |
| 94 | + ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT)) |
| 95 | + |
| 96 | +#define STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHAN, INV) \ |
| 97 | + ((int)(FUNC_OD) |\ |
| 98 | + ((PUPD & STM_PIN_PUPD_MASK) << STM_PIN_PUPD_SHIFT) |\ |
| 99 | + ((AFNUM & STM_PIN_AFNUM_MASK) << STM_PIN_AFNUM_SHIFT) |\ |
| 100 | + ((CHAN & STM_PIN_CHAN_MASK) << STM_PIN_CHAN_SHIFT) |\ |
| 101 | + ((INV & STM_PIN_INV_MASK) << STM_PIN_INV_SHIFT)) |
| 102 | + |
| 103 | +/* |
| 104 | + * MACROS to support the legacy definition of PIN formats |
| 105 | + * The STM_MODE_ defines contain the function and the Push-pull/OpenDrain |
| 106 | + * configuration (legacy inheritance). |
| 107 | + */ |
| 108 | +#define STM_PIN_DATA(FUNC_OD, PUPD, AFNUM) \ |
| 109 | + STM_PIN_DEFINE(FUNC_OD, PUPD, AFNUM) |
| 110 | +#define STM_PIN_DATA_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED) \ |
| 111 | + STM_PIN_DEFINE_EXT(FUNC_OD, PUPD, AFNUM, CHANNEL, INVERTED) |
| 112 | + |
| 113 | +typedef enum { |
| 114 | + STM_PIN_INPUT = 0, |
| 115 | + STM_PIN_OUTPUT = 1, |
| 116 | + STM_PIN_ALTERNATE = 2, |
| 117 | + STM_PIN_ANALOG = 3, |
| 118 | +} StmPinFunction; |
| 119 | + |
| 120 | +#define STM_MODE_INPUT (STM_PIN_INPUT) |
| 121 | +#define STM_MODE_OUTPUT_PP (STM_PIN_OUTPUT) |
| 122 | +#define STM_MODE_OUTPUT_OD (STM_PIN_OUTPUT | STM_PIN_OD_BITS) |
| 123 | +#define STM_MODE_AF_PP (STM_PIN_ALTERNATE) |
| 124 | +#define STM_MODE_AF_OD (STM_PIN_ALTERNATE | STM_PIN_OD_BITS) |
| 125 | +#define STM_MODE_ANALOG (STM_PIN_ANALOG) |
| 126 | +#define STM_MODE_ANALOG_ADC_CONTROL (STM_PIN_ANALOG | STM_PIN_ANALOG_CONTROL_BIT) |
70 | 127 |
|
71 | 128 | // High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
|
72 | 129 | // Low nibble = pin number
|
73 | 130 | #define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
|
74 | 131 | #define STM_PIN(X) ((uint32_t)(X) & 0xF)
|
75 | 132 |
|
| 133 | +/* Defines to be used by application */ |
76 | 134 | typedef enum {
|
77 |
| - PIN_INPUT, |
| 135 | + PIN_INPUT = 0, |
78 | 136 | PIN_OUTPUT
|
79 | 137 | } PinDirection;
|
80 | 138 |
|
81 | 139 | typedef enum {
|
82 |
| - PullNone = 0, |
83 |
| - PullUp = 1, |
84 |
| - PullDown = 2, |
85 |
| - OpenDrain = 3, |
86 |
| - PullDefault = PullNone |
| 140 | + PullNone = 0, |
| 141 | + PullUp = 1, |
| 142 | + PullDown = 2, |
| 143 | + OpenDrainPullUp = 3, |
| 144 | + OpenDrainNoPull = 4, |
| 145 | + OpenDrainPullDown = 5, |
| 146 | + PushPullNoPull = PullNone, |
| 147 | + PushPullPullUp = PullUp, |
| 148 | + PushPullPullDown = PullDown, |
| 149 | + OpenDrain = OpenDrainPullUp, |
| 150 | + PullDefault = PullNone |
87 | 151 | } PinMode;
|
88 | 152 |
|
89 | 153 | #ifdef __cplusplus
|
90 | 154 | }
|
91 | 155 | #endif
|
92 | 156 |
|
93 | 157 | #endif
|
| 158 | + |
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