Skip to content

Commit b964420

Browse files
author
Marcus Chang
committed
Reorganize targets.json for NRF52 based targets
* Consolidated device_has and macros to the main MCU targets. * Moved errata configuration to mbed_lib.json for HAL implementation. * Moved clock configuration to mbed_lib.json for HAL implementation. * Moved UART configuration to mbed_lib.json for HAL implementation.
1 parent 2c651af commit b964420

File tree

10 files changed

+322
-138
lines changed

10 files changed

+322
-138
lines changed

‎targets/TARGET_NORDIC/TARGET_NRF5x/README.md

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,52 @@
1+
# Nordic NRF52
2+
3+
## Adding New Targets Based On Nordic NRF52832 And NRF52840 MCUs
4+
5+
First, create a new entry in `mbed-os/targets/targets.json` using the template below:
6+
7+
```json
8+
{
9+
"target_name": {
10+
"inherits": [""],
11+
"release_versions": ["5"],
12+
"device_name": ""
13+
},
14+
}
15+
```
16+
17+
Where `target_name` is the name of the new target, `inherits` can be either `MCU_NRF52832` or `MCU_NRF52840`, and `device_name` is the ID specifying actual RAM and flash size, for example, `nRF52832_xxAA` and `nRF52840_xxAA`. The `release_version` specifies that the target is compatible with Mbed OS 5.
18+
19+
This entry enables the new target in the Mbed OS build system.
20+
21+
Next, add optional target specific configuration in `mbed-os/targets/TARGET_NORDIC/TARGET_NRF5x/mbed_lib.json`.
22+
23+
```json
24+
{
25+
"target_overrides": {
26+
"target_name": {
27+
"target.macros_add": [
28+
"optional macros"
29+
],
30+
"optional configuration"
31+
}
32+
}
33+
}
34+
```
35+
36+
The optional configuration includes specifying errata fixes specific for the MCU release used on the target, configuring the low-frequency clock source, and configuring the UART behavior. See targets `NRF52_DK` and `NRF52840_DK` for examples.
37+
38+
### LF Clock Configuration
39+
40+
LF clock source configuration is used for MCU startup initialization and the BLE SoftDevice LF clock configuration (if BLE libraries is used). Advanced configurations are used only for the BLE SoftDevice LF clock configuration.
41+
42+
Default clock source is XTAL oscillator. There are three options that can be configured as the clock source:
43+
- NRF_LF_SRC_XTAL
44+
- NRF_LF_SRC_RC
45+
- NRF_LF_SRC_SYNTH
46+
47+
Set `lf_clock_src` to what is most suitable for the target. This value can later be overridden by the user application if necessary.
48+
49+
150
## Mbed HAL Implementation Details
251

352
### SPI and I2C

‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/PinNames.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,8 @@ typedef enum {
201201
USBRX = RX_PIN_NUMBER,
202202
STDIO_UART_TX = TX_PIN_NUMBER,
203203
STDIO_UART_RX = RX_PIN_NUMBER,
204+
STDIO_UART_CTS = CTS_PIN_NUMBER,
205+
STDIO_UART_RTS = RTS_PIN_NUMBER,
204206

205207
SPI_MOSI = SIO_23,
206208
SPI_MISO = SIO_24,

‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_NRF52_DK/PinNames.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -142,6 +142,8 @@ typedef enum {
142142
USBRX = RX_PIN_NUMBER,
143143
STDIO_UART_TX = TX_PIN_NUMBER,
144144
STDIO_UART_RX = RX_PIN_NUMBER,
145+
STDIO_UART_CTS = CTS_PIN_NUMBER,
146+
STDIO_UART_RTS = RTS_PIN_NUMBER,
145147

146148
SPI_PSELMOSI0 = p23,
147149
SPI_PSELMISO0 = p24,

‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_UBLOX_EVK_NINA_B1/PinNames.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,8 @@ typedef enum {
109109
RTS_PIN_NUMBER = p31,
110110
STDIO_UART_TX = TX_PIN_NUMBER,
111111
STDIO_UART_RX = RX_PIN_NUMBER,
112+
STDIO_UART_CTS = CTS_PIN_NUMBER,
113+
STDIO_UART_RTS = RTS_PIN_NUMBER,
112114
I2C_SDA0 = p2,
113115
I2C_SCL0 = p3,
114116
// mBed interface pins

‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52832/TARGET_VBLUNO52/PinNames.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -143,6 +143,8 @@ typedef enum {
143143
RTS_PIN_NUMBER = p5, //not on Header
144144
STDIO_UART_TX = TX_PIN_NUMBER,
145145
STDIO_UART_RX = RX_PIN_NUMBER,
146+
STDIO_UART_CTS = CTS_PIN_NUMBER,
147+
STDIO_UART_RTS = RTS_PIN_NUMBER,
146148

147149
// mBed interface Pins
148150
USBTX = TX_PIN_NUMBER,

‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/TARGET_MCU_NRF52840/TARGET_NRF52840_DK/PinNames.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -180,6 +180,8 @@ typedef enum {
180180
USBRX = RX_PIN_NUMBER,
181181
STDIO_UART_TX = TX_PIN_NUMBER,
182182
STDIO_UART_RX = RX_PIN_NUMBER,
183+
STDIO_UART_CTS = CTS_PIN_NUMBER,
184+
STDIO_UART_RTS = RTS_PIN_NUMBER,
183185

184186
SPI_PSELMOSI0 = P1_13,
185187
SPI_PSELMISO0 = P1_14,

‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_14_2/TARGET_SOFTDEVICE_S132/mbed_lib.json

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,11 @@
11
{
22
"name": "softdevice",
33
"config": {
4-
"comment": {
5-
"help": "S132, BLE_STACK_SUPPORT_REQD: These macros are currently defined in target.json but should be moved here.",
6-
"value": null
7-
}
84
},
95
"macros": [
106
"SOFTDEVICE_PRESENT=1",
7+
"S132",
8+
"BLE_STACK_SUPPORT_REQD",
119
"NRF_SDH_CLOCK_LF_SRC=1",
1210
"NRF_SDH_CLOCK_LF_RC_CTIV=0",
1311
"NRF_SDH_CLOCK_LF_RC_TEMP_CTIV=0",

‎targets/TARGET_NORDIC/TARGET_NRF5x/mbed_lib.json

Lines changed: 182 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,199 @@
11
{
22
"name": "nordic",
33
"config": {
4-
"uart-hwfc": {
5-
"help": "Enable hardware flow control for STDIO.",
6-
"value": 1
7-
},
8-
"lf-clock-src": {
9-
"help": "Select Low Frequency clock source.",
10-
"value": "NRF_LF_SRC_XTAL"
11-
},
12-
"uart-timeout-us": {
4+
"uart_timeout_us": {
135
"help": "Idle time in micro seconds between characters before buffer is flushed.",
146
"value": 2000
157
},
16-
"uart-0-fifo-size": {
8+
"uart_0_fifo_size": {
179
"help": "UART0 FIFO buffer. FIFO buffer is filled from DMA buffer.",
1810
"value": 32
1911
},
20-
"uart-1-fifo-size": {
12+
"uart_1_fifo_size": {
2113
"help": "UART1 FIFO buffer. FIFO buffer is filled from DMA buffer.",
2214
"value": 32
2315
},
24-
"uart-dma-size": {
16+
"uart_dma_size": {
2517
"help": "UART DMA buffer. 2 buffers per instance. DMA buffer is filled by UARTE",
2618
"value": 8
2719
}
20+
},
21+
"target_overrides": {
22+
"DELTA_DFBM_NQ620": {
23+
"target.macros_add": [
24+
"CONFIG_GPIO_AS_PINRESET",
25+
"SWI_DISABLE0",
26+
"NRF52_PAN_12",
27+
"NRF52_PAN_15",
28+
"NRF52_PAN_20",
29+
"NRF52_PAN_30",
30+
"NRF52_PAN_31",
31+
"NRF52_PAN_36",
32+
"NRF52_PAN_51",
33+
"NRF52_PAN_53",
34+
"NRF52_PAN_54",
35+
"NRF52_PAN_55",
36+
"NRF52_PAN_58",
37+
"NRF52_PAN_62",
38+
"NRF52_PAN_63",
39+
"NRF52_PAN_64"
40+
],
41+
"target.lf_clock_src": "NRF_LF_SRC_RC",
42+
"target.lf_clock_rc_calib_timer_interval": 16,
43+
"target.lf_clock_rc_calib_mode_config": 0
44+
},
45+
"MTB_LAIRD_BL652": {
46+
"target.macros_add": [
47+
"CONFIG_GPIO_AS_PINRESET",
48+
"SWI_DISABLE0",
49+
"NRF52_PAN_12",
50+
"NRF52_PAN_15",
51+
"NRF52_PAN_20",
52+
"NRF52_PAN_30",
53+
"NRF52_PAN_31",
54+
"NRF52_PAN_36",
55+
"NRF52_PAN_51",
56+
"NRF52_PAN_53",
57+
"NRF52_PAN_54",
58+
"NRF52_PAN_55",
59+
"NRF52_PAN_58",
60+
"NRF52_PAN_62",
61+
"NRF52_PAN_63",
62+
"NRF52_PAN_64"
63+
],
64+
"target.lf_clock_src": "NRF_LF_SRC_RC",
65+
"target.console-uart-flow-control": "RTSCTS"
66+
},
67+
"MTB_UBLOX_NINA_B1": {
68+
"target.macros_add": [
69+
"CONFIG_GPIO_AS_PINRESET",
70+
"SWI_DISABLE0",
71+
"NRF52_PAN_12",
72+
"NRF52_PAN_15",
73+
"NRF52_PAN_20",
74+
"NRF52_PAN_30",
75+
"NRF52_PAN_31",
76+
"NRF52_PAN_36",
77+
"NRF52_PAN_51",
78+
"NRF52_PAN_53",
79+
"NRF52_PAN_54",
80+
"NRF52_PAN_55",
81+
"NRF52_PAN_58",
82+
"NRF52_PAN_62",
83+
"NRF52_PAN_63",
84+
"NRF52_PAN_64"
85+
]
86+
},
87+
"NRF52_DK": {
88+
"target.macros_add": [
89+
"CONFIG_GPIO_AS_PINRESET",
90+
"SWI_DISABLE0",
91+
"NRF52_PAN_12",
92+
"NRF52_PAN_15",
93+
"NRF52_PAN_20",
94+
"NRF52_PAN_30",
95+
"NRF52_PAN_31",
96+
"NRF52_PAN_36",
97+
"NRF52_PAN_51",
98+
"NRF52_PAN_53",
99+
"NRF52_PAN_54",
100+
"NRF52_PAN_55",
101+
"NRF52_PAN_58",
102+
"NRF52_PAN_62",
103+
"NRF52_PAN_63",
104+
"NRF52_PAN_64"
105+
],
106+
"target.console-uart-flow-control": "RTSCTS"
107+
},
108+
"RBLAB_BLENANO2": {
109+
"target.macros_add": [
110+
"CONFIG_GPIO_AS_PINRESET",
111+
"SWI_DISABLE0",
112+
"NRF52_PAN_12",
113+
"NRF52_PAN_15",
114+
"NRF52_PAN_20",
115+
"NRF52_PAN_30",
116+
"NRF52_PAN_31",
117+
"NRF52_PAN_36",
118+
"NRF52_PAN_51",
119+
"NRF52_PAN_53",
120+
"NRF52_PAN_54",
121+
"NRF52_PAN_55",
122+
"NRF52_PAN_58",
123+
"NRF52_PAN_62",
124+
"NRF52_PAN_63",
125+
"NRF52_PAN_64"
126+
]
127+
},
128+
"UBLOX_EVA_NINA": {
129+
"target.macros_add": [
130+
"CONFIG_GPIO_AS_PINRESET",
131+
"SWI_DISABLE0",
132+
"NRF52_PAN_12",
133+
"NRF52_PAN_15",
134+
"NRF52_PAN_20",
135+
"NRF52_PAN_30",
136+
"NRF52_PAN_31",
137+
"NRF52_PAN_36",
138+
"NRF52_PAN_51",
139+
"NRF52_PAN_53",
140+
"NRF52_PAN_54",
141+
"NRF52_PAN_55",
142+
"NRF52_PAN_58",
143+
"NRF52_PAN_62",
144+
"NRF52_PAN_63",
145+
"NRF52_PAN_64"
146+
]
147+
},
148+
"UBLOX_EVK_NINA_B1": {
149+
"target.macros_add": [
150+
"CONFIG_GPIO_AS_PINRESET",
151+
"SWI_DISABLE0",
152+
"NRF52_PAN_12",
153+
"NRF52_PAN_15",
154+
"NRF52_PAN_20",
155+
"NRF52_PAN_30",
156+
"NRF52_PAN_31",
157+
"NRF52_PAN_36",
158+
"NRF52_PAN_51",
159+
"NRF52_PAN_53",
160+
"NRF52_PAN_54",
161+
"NRF52_PAN_55",
162+
"NRF52_PAN_58",
163+
"NRF52_PAN_62",
164+
"NRF52_PAN_63",
165+
"NRF52_PAN_64"
166+
],
167+
"target.console-uart-flow-control": "RTSCTS"
168+
},
169+
"VBLUNO52": {
170+
"target.macros_add": [
171+
"CONFIG_GPIO_AS_PINRESET",
172+
"SWI_DISABLE0",
173+
"NRF52_PAN_12",
174+
"NRF52_PAN_15",
175+
"NRF52_PAN_20",
176+
"NRF52_PAN_30",
177+
"NRF52_PAN_31",
178+
"NRF52_PAN_36",
179+
"NRF52_PAN_51",
180+
"NRF52_PAN_53",
181+
"NRF52_PAN_54",
182+
"NRF52_PAN_55",
183+
"NRF52_PAN_58",
184+
"NRF52_PAN_62",
185+
"NRF52_PAN_63",
186+
"NRF52_PAN_64"
187+
],
188+
"target.console-uart-flow-control": "RTSCTS"
189+
},
190+
"NRF52840_DK": {
191+
"target.macros_add": [
192+
"CONFIG_GPIO_AS_PINRESET",
193+
"SWI_DISABLE0",
194+
"NRF52_ERRATA_20"
195+
],
196+
"target.console-uart-flow-control": "RTSCTS"
197+
}
28198
}
29199
}

‎targets/TARGET_NORDIC/TARGET_NRF5x/serial_api.c

Lines changed: 3 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -66,13 +66,6 @@
6666
* |___/
6767
*/
6868

69-
/**
70-
* Legacy hardware flow control setting. Enables flow control for STDOUT.
71-
*/
72-
#ifndef MBED_CONF_NORDIC_UART_HWFC
73-
#define MBED_CONF_NORDIC_UART_HWFC 0
74-
#endif
75-
7669
/**
7770
* Idle timeout between characters before DMA buffer is flushed.
7871
*/
@@ -1056,23 +1049,9 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
10561049
/* Set default parity and baud rate. */
10571050
uart_object->parity = NRF_UART_PARITY_EXCLUDED;
10581051
uart_object->baudrate = NRF_UART_BAUDRATE_9600;
1059-
1060-
/**
1061-
* If the provided pins match STDOUT and the default flow control is enabled,
1062-
* enable flow control using STDOUT's flow control pins.
1063-
*/
1064-
if (MBED_CONF_NORDIC_UART_HWFC && (tx == STDIO_UART_TX) && (rx == STDIO_UART_RX)) {
1065-
1066-
uart_object->cts = CTS_PIN_NUMBER;
1067-
uart_object->rts = RTS_PIN_NUMBER;
1068-
uart_object->hwfc = NRF_UART_HWFC_ENABLED;
1069-
1070-
} else {
1071-
1072-
uart_object->cts = NRF_UART_PSEL_DISCONNECTED;
1073-
uart_object->rts = NRF_UART_PSEL_DISCONNECTED;
1074-
uart_object->hwfc = NRF_UART_HWFC_DISABLED;
1075-
}
1052+
uart_object->cts = NRF_UART_PSEL_DISCONNECTED;
1053+
uart_object->rts = NRF_UART_PSEL_DISCONNECTED;
1054+
uart_object->hwfc = NRF_UART_HWFC_DISABLED;
10761055

10771056
/* The STDIO object is stored in this file. Set the flag once initialized. */
10781057
if (obj == &stdio_uart) {

0 commit comments

Comments
 (0)