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theotherjimmytheotherjimmy
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Merge pull request #4638 from bcostm/fix_cmsis5_disco_l475vg
DISCO_L475VG_IOT01A: Fix startup files for cmsis5
2 parents b89fd03 + 03930b8 commit bb3beda

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6 files changed

+84
-26
lines changed

6 files changed

+84
-26
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‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_DISCO_L475VG_IOT01A/system_stm32l4xx.c

Lines changed: 2 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@
8383
*/
8484

8585
#include "stm32l4xx.h"
86-
#include "hal_tick.h"
86+
#include "nvic_addr.h"
8787

8888
#if !defined (HSE_VALUE)
8989
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
@@ -215,20 +215,9 @@ void SystemInit(void)
215215
#ifdef VECT_TAB_SRAM
216216
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
217217
#else
218-
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
218+
SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
219219
#endif
220220

221-
/* Configure the Cube driver */
222-
SystemCoreClock = MSI_VALUE; // At this stage the MSI is used as system clock
223-
HAL_Init();
224-
225-
/* Configure the System clock source, PLL Multiplier and Divider factors,
226-
AHB/APBx prescalers and Flash settings */
227-
SetSysClock();
228-
229-
/* Reset the timer to avoid issues after the RAM initialization */
230-
TIM_MST_RESET_ON;
231-
TIM_MST_RESET_OFF;
232221
}
233222

234223
/**

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_MICRO/stm32l475xx.sct

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
#! armcc -E
12
; Scatter-Loading Description File
23
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
34
; Copyright (c) 2015, STMicroelectronics
@@ -27,10 +28,18 @@
2728
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2829
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2930

31+
#if !defined(MBED_APP_START)
32+
#define MBED_APP_START 0x08000000
33+
#endif
34+
35+
#if !defined(MBED_APP_SIZE)
36+
#define MBED_APP_SIZE 0x100000
37+
#endif
38+
3039
; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
31-
LR_IROM1 0x08000000 0x100000 { ; load region size_region
40+
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
3241

33-
ER_IROM1 0x08000000 0x100000 { ; load address = execution address
42+
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
3443
*.o (RESET, +First)
3544
*(InRoot$$Sections)
3645
.ANY (+RO)

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_ARM_STD/stm32l475xx.sct

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
#! armcc -E
12
; Scatter-Loading Description File
23
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
34
; Copyright (c) 2015, STMicroelectronics
@@ -27,10 +28,18 @@
2728
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2829
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2930

31+
#if !defined(MBED_APP_START)
32+
#define MBED_APP_START 0x08000000
33+
#endif
34+
35+
#if !defined(MBED_APP_SIZE)
36+
#define MBED_APP_SIZE 0x100000
37+
#endif
38+
3039
; 1MB FLASH (0x100000) + 128KB SRAM (0x20000)
31-
LR_IROM1 0x08000000 0x100000 { ; load region size_region
40+
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
3241

33-
ER_IROM1 0x08000000 0x100000 { ; load address = execution address
42+
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
3443
*.o (RESET, +First)
3544
*(InRoot$$Sections)
3645
.ANY (+RO)

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,15 @@
1+
#if !defined(MBED_APP_START)
2+
#define MBED_APP_START 0x08000000
3+
#endif
4+
5+
#if !defined(MBED_APP_SIZE)
6+
#define MBED_APP_SIZE 1024k
7+
#endif
8+
19
/* Linker script to configure memory regions. */
210
MEMORY
311
{
4-
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
12+
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
513
SRAM2 (rwx) : ORIGIN = 0x10000188, LENGTH = 32k - 0x188
614
SRAM1 (rwx) : ORIGIN = 0x20000000, LENGTH = 96k
715
}

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_IAR/stm32l475xx.icf

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,16 @@
1+
if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
2+
if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
3+
14
/* [ROM = 1024kb = 0x100000] */
2-
define symbol __intvec_start__ = 0x08000000;
3-
define symbol __region_ROM_start__ = 0x08000000;
4-
define symbol __region_ROM_end__ = 0x080FFFFF;
5+
define symbol __intvec_start__ = MBED_APP_START;
6+
define symbol __region_ROM_start__ = MBED_APP_START;
7+
define symbol __region_ROM_end__ = MBED_APP_START + MBED_APP_SIZE - 1;
58

6-
/* [RAM = 128kb = 96kb + 32kb = 0x20000] */
9+
/* [RAM = 96kb + 32kb = 0x20000] */
710
/* Vector table dynamic copy: Total: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
811
define symbol __NVIC_start__ = 0x10000000;
9-
define symbol __NVIC_end__ = 0x10000187;
10-
define symbol __region_SRAM2_start__ = 0x10000188; /* This adress is 8-byte aligned */
12+
define symbol __NVIC_end__ = 0x10000187; /* Aligned on 8 bytes (392 = 49 x 8) */
13+
define symbol __region_SRAM2_start__ = 0x10000188;
1114
define symbol __region_SRAM2_end__ = 0x10007FFF;
1215
define symbol __region_SRAM1_start__ = 0x20000000;
1316
define symbol __region_SRAM1_end__ = 0x20017FFF;
@@ -31,5 +34,5 @@ do not initialize { section .noinit };
3134
place at address mem:__intvec_start__ { readonly section .intvec };
3235

3336
place in ROM_region { readonly };
34-
place in SRAM1_region { readwrite, block STACKHEAP };
35-
place in SRAM2_region { };
37+
place in SRAM1_region { readwrite, block STACKHEAP };
38+
place in SRAM2_region { };

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/nvic_addr.h

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
1+
/* mbed Microcontroller Library
2+
* Copyright (c) 2017-2017 ARM Limited
3+
*
4+
* Licensed under the Apache License, Version 2.0 (the "License");
5+
* you may not use this file except in compliance with the License.
6+
* You may obtain a copy of the License at
7+
*
8+
* http://www.apache.org/licenses/LICENSE-2.0
9+
*
10+
* Unless required by applicable law or agreed to in writing, software
11+
* distributed under the License is distributed on an "AS IS" BASIS,
12+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13+
* See the License for the specific language governing permissions and
14+
* limitations under the License.
15+
*/
16+
#ifndef NVIC_ADDR_H
17+
#define NVIC_ADDR_H
18+
19+
#ifdef __cplusplus
20+
extern "C" {
21+
#endif
22+
23+
#if defined(__ICCARM__)
24+
#pragma section=".intvec"
25+
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)__section_begin(".intvec"))
26+
#elif defined(__CC_ARM)
27+
extern uint32_t Load$$LR$$LR_IROM1$$Base[];
28+
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)Load$$LR$$LR_IROM1$$Base)
29+
#elif defined(__GNUC__)
30+
extern uint32_t g_pfnVectors[];
31+
#define NVIC_FLASH_VECTOR_ADDRESS ((uint32_t)g_pfnVectors)
32+
#else
33+
#error "Flash vector address not set for this toolchain"
34+
#endif
35+
36+
#ifdef __cplusplus
37+
}
38+
#endif
39+
40+
#endif

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