QSPI : Define default pins at drivers level

Author: jeromecoutant

TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

@@ -17,6 +17,16 @@
 #ifndef MBED_FLASH_CONFIGS_H
 #define MBED_FLASH_CONFIGS_H
 
+#define MX25R6435F 1
+
+#if defined(QSPI_FLASH_CHIP)
+
+#if (QSPI_FLASH_CHIP == MX25R6435F)
+#include "MX25RXX35F_config.h"
+#endif
+
+#else // QSPI_FLASH_CHIP not defined
+
 #if defined(TARGET_DISCO_L475VG_IOT01A)
 #include "MX25RXX35F_config.h" // MX25R6435F
 
@@ -88,5 +98,6 @@
 #include "S25FL128S_config.h"
 
 #endif
+#endif // QSPI_FLASH_CHIP
 #endif // MBED_FLASH_CONFIGS_H
 

TESTS/mbed_hal/qspi/main.cpp

@@ -70,12 +70,12 @@ uint8_t rx_buf[DATA_SIZE_1024];
 
 
 // some target defines QSPI pins as integers thus conversion needed
-#define QPIN_0 static_cast<PinName>(QSPI_FLASH1_IO0)
-#define QPIN_1 static_cast<PinName>(QSPI_FLASH1_IO1)
-#define QPIN_2 static_cast<PinName>(QSPI_FLASH1_IO2)
-#define QPIN_3 static_cast<PinName>(QSPI_FLASH1_IO3)
-#define QSCK   static_cast<PinName>(QSPI_FLASH1_SCK)
-#define QCSN   static_cast<PinName>(QSPI_FLASH1_CSN)
+#define QPIN_0 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO0)
+#define QPIN_1 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO1)
+#define QPIN_2 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO2)
+#define QPIN_3 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO3)
+#define QSCK   static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_SCK)
+#define QCSN   static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_CSN)
 
 
 static uint32_t gen_flash_address()

components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json

@@ -1,12 +1,12 @@
 {
 "name": "qspif",
     "config": {
-        "QSPI_IO0": "QSPI_FLASH1_IO0",
-        "QSPI_IO1": "QSPI_FLASH1_IO1",
-        "QSPI_IO2": "QSPI_FLASH1_IO2",
-        "QSPI_IO3": "QSPI_FLASH1_IO3",
-        "QSPI_SCK": "QSPI_FLASH1_SCK",
-        "QSPI_CSN": "QSPI_FLASH1_CSN",
+        "QSPI_IO0": "MBED_CONF_DRIVERS_QSPI_IO0",
+        "QSPI_IO1": "MBED_CONF_DRIVERS_QSPI_IO1",
+        "QSPI_IO2": "MBED_CONF_DRIVERS_QSPI_IO2",
+        "QSPI_IO3": "MBED_CONF_DRIVERS_QSPI_IO3",
+        "QSPI_SCK": "MBED_CONF_DRIVERS_QSPI_SCK",
+        "QSPI_CSN": "MBED_CONF_DRIVERS_QSPI_CSN",
         "QSPI_POLARITY_MODE": 0,
         "QSPI_FREQ": "40000000",
         "QSPI_MIN_READ_SIZE": "1",

drivers/mbed_lib.json

@@ -12,6 +12,24 @@
         "spi_count_max": {
             "help": "The maximum number of SPI peripherals used at the same time. Determines RAM allocated for SPI peripheral management. If null, limit determined by hardware.",
             "value": null
+        },
+        "qspi_io0": {
+            "value": "QSPI_FLASH1_IO0"
+        },
+        "qspi_io1": {
+            "value": "QSPI_FLASH1_IO1"
+        },
+        "qspi_io2": {
+            "value": "QSPI_FLASH1_IO2"
+        },
+        "qspi_io3": {
+            "value": "QSPI_FLASH1_IO3"
+        },
+        "qspi_sck": {
+            "value": "QSPI_FLASH1_SCK"
+        },
+        "qspi_csn": {
+            "value": "QSPI_FLASH1_CSN"
         }
     }
 }