Skip to content

Commit bd499da

Browse files
0xc01700xc0170
authored
Merge pull request #3304 from jeromecoutant/PR_L476
STM32L476: no HSE is present in NUCLEO and DISCO boards
2 parents 1c2c121 + 448f501 commit bd499da

File tree

2 files changed

+66
-62
lines changed

2 files changed

+66
-62
lines changed

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device/system_stm32l4xx.c

Lines changed: 26 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -26,21 +26,19 @@
2626
*
2727
* This file configures the system clock as follows:
2828
*=============================================================================
29-
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
30-
* | (external 8 MHz clock) | (internal 16 MHz)
31-
* | 2- PLL_HSE_XTAL | or PLL_MSI
32-
* | (external 8 MHz xtal) | (internal 4 MHz)
33-
*-----------------------------------------------------------------------------
34-
* SYSCLK(MHz) | 48 | 80
35-
*-----------------------------------------------------------------------------
36-
* AHBCLK (MHz) | 48 | 80
37-
*-----------------------------------------------------------------------------
38-
* APB1CLK (MHz) | 48 | 80
39-
*-----------------------------------------------------------------------------
40-
* APB2CLK (MHz) | 48 | 80
41-
*-----------------------------------------------------------------------------
42-
* USB capable (48 MHz precise clock) | YES | NO
43-
*-----------------------------------------------------------------------------
29+
* System clock source | PLL_HSE | PLL_HSI | PLL_MSI
30+
* | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
31+
*---------------------------------------------------------------------------------------------
32+
* SYSCLK(MHz) | 48 | 80 | 80
33+
*---------------------------------------------------------------------------------------------
34+
* AHBCLK (MHz) | 48 | 80 | 80
35+
*---------------------------------------------------------------------------------------------
36+
* APB1CLK (MHz) | 48 | 80 | 80
37+
*---------------------------------------------------------------------------------------------
38+
* APB2CLK (MHz) | 48 | 80 | 80
39+
*---------------------------------------------------------------------------------------------
40+
* USB capable (48 MHz precise clock) | YES | NO | YES
41+
*---------------------------------------------------------------------------------------------
4442
*=============================================================================
4543
******************************************************************************
4644
* @attention
@@ -131,7 +129,7 @@
131129
*/
132130

133131
// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
134-
#define USE_PLL_HSE_EXTC (1) // Use external clock
132+
#define USE_PLL_HSE_EXTC (0) // Use external clock
135133
#define USE_PLL_HSE_XTAL (0) // Use external xtal
136134
#define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
137135
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
@@ -547,15 +545,15 @@ uint8_t SetSysClock_PLL_MSI(void)
547545
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
548546
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
549547

550-
RCC_OscInitStruct.HSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
551-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
548+
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
549+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
552550
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
553551
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
554-
RCC_OscInitStruct.PLL.PLLM = 6;
555-
RCC_OscInitStruct.PLL.PLLN = 40;
556-
RCC_OscInitStruct.PLL.PLLP = 7;
557-
RCC_OscInitStruct.PLL.PLLQ = 4;
558-
RCC_OscInitStruct.PLL.PLLR = 4;
552+
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
553+
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
554+
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
555+
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
556+
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
559557
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
560558
{
561559
return 0; // FAIL
@@ -564,14 +562,14 @@ uint8_t SetSysClock_PLL_MSI(void)
564562
HAL_RCCEx_EnableMSIPLLMode();
565563
/* Select MSI output as USB clock source */
566564
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
567-
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
565+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
568566
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
569567
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
570568
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
571-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
572-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
573-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
574-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 80 MHz
569+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
570+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
571+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
572+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; /* 40 MHz */
575573
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
576574
{
577575
return 0; // FAIL

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_L476_L486/device/system_stm32l4xx.c

Lines changed: 40 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -26,21 +26,19 @@
2626
*
2727
* This file configures the system clock as follows:
2828
*=============================================================================
29-
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
30-
* | (external 8 MHz clock) | (internal 16 MHz)
31-
* | 2- PLL_HSE_XTAL | or PLL_MSI
32-
* | (external 8 MHz xtal) | (internal 4 MHz)
33-
*-----------------------------------------------------------------------------
34-
* SYSCLK(MHz) | 48 | 80
35-
*-----------------------------------------------------------------------------
36-
* AHBCLK (MHz) | 48 | 80
37-
*-----------------------------------------------------------------------------
38-
* APB1CLK (MHz) | 48 | 80
39-
*-----------------------------------------------------------------------------
40-
* APB2CLK (MHz) | 48 | 80
41-
*-----------------------------------------------------------------------------
42-
* USB capable (48 MHz precise clock) | YES | NO
43-
*-----------------------------------------------------------------------------
29+
* System clock source | PLL_HSE | PLL_HSI | PLL_MSI
30+
* | (external 4 to 48 MHz xtal) | (internal 16 MHz) | (internal 100kHz to 48 MHz)
31+
*---------------------------------------------------------------------------------------------
32+
* SYSCLK(MHz) | 48 | 80 | 80
33+
*---------------------------------------------------------------------------------------------
34+
* AHBCLK (MHz) | 48 | 80 | 80
35+
*---------------------------------------------------------------------------------------------
36+
* APB1CLK (MHz) | 48 | 80 | 80
37+
*---------------------------------------------------------------------------------------------
38+
* APB2CLK (MHz) | 48 | 80 | 80
39+
*---------------------------------------------------------------------------------------------
40+
* USB capable (48 MHz precise clock) | YES | NO | YES
41+
*---------------------------------------------------------------------------------------------
4442
*=============================================================================
4543
******************************************************************************
4644
* @attention
@@ -131,7 +129,7 @@
131129
*/
132130

133131
// Select the clock sources (default is PLL_MSI) to start with (0=OFF, 1=ON)
134-
#define USE_PLL_HSE_EXTC (1) // Use external clock
132+
#define USE_PLL_HSE_EXTC (0) // Use external clock
135133
#define USE_PLL_HSE_XTAL (0) // Use external xtal
136134
#define USE_PLL_HSI (0) // Use HSI/MSI internal clock (0=MSI, 1=HSI)
137135
#define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
@@ -530,40 +528,48 @@ uint8_t SetSysClock_PLL_MSI(void)
530528
{
531529
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
532530
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
533-
531+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
532+
534533
// Enable LSE Oscillator to automatically calibrate the MSI clock
535534
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
536535
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
537536
RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
538537
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
539538
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
540539
}
541-
542-
// Enable MSI oscillator and activate PLL with MSI as source
543-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
540+
541+
HAL_RCCEx_DisableLSECSS();
542+
/* Enable MSI Oscillator and activate PLL with MSI as source */
543+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
544544
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
545545
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
546546
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
547-
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
548-
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
549-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
550-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; // 4 MHz
551-
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 4 MHz (4 MHz / 1)
552-
RCC_OscInitStruct.PLL.PLLN = 40; // VCO output clock = 160 MHz (4 MHz * 40)
553-
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22.86 MHz (160 MHz / 7)
554-
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
555-
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
547+
548+
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
549+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */
550+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
551+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
552+
RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */
553+
RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */
554+
RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */
555+
RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */
556+
RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */
556557
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
557558
{
558559
return 0; // FAIL
559560
}
560-
561+
/* Enable MSI Auto-calibration through LSE */
562+
HAL_RCCEx_EnableMSIPLLMode();
563+
/* Select MSI output as USB clock source */
564+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
565+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
566+
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
561567
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
562568
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
563-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
564-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
565-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
566-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
569+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
570+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */
571+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */
572+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; /* 40 MHz */
567573
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
568574
{
569575
return 0; // FAIL

0 commit comments

Comments
 (0)