Revise startup processing having CMSIS5/RTX5 been available on GR-PEACH

For supporting tp CMSIS5/RTX5, I changed the start-up processing of 3 toolchains(ARMCC, GCC_ARM, IAR) and updated the register definition of PEACH specific.
In addition,
I changed the linker script files to implement the dynamic HEAP the same as Cortex-M targets.Since GR-PEACH's HEAP was a fixed area, I changed the label name(ZI_DATA to RW_IRAM1) and replaced the allocation of STACK/HEAP.

Author: TomoYamanaka

targets/TARGET_RENESAS/TARGET_RZ_A1H/device/MBRZA1H.h

@@ -1,43 +1,57 @@
+#! armcc -E
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
 
+; Scatter-file for RTX Example on Versatile Express
 
-LOAD_TTB    0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+#include "mem_RZ_A1H.h"
+
+LOAD_TTB    __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
 {
     TTB     +0 EMPTY 0x4000            
     { }                           ; Level-1 Translation Table for MMU
 }
 
-SFLASH 0x18000000 (0x08000000)
+SFLASH __ROM_BASE __ROM_SIZE       ; load region size_region
 {
-    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-    ; S-Flash ROM : Executable cached region
-    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+  BOOT_LOADER_BEGIN __ROM_BASE FIXED
+  {
+    * (BOOT_LOADER)
+  }
 
-    BOOT_LOADER_BEGIN 0x18000000 FIXED
-    {
-        *   ( BOOT_LOADER )
-    }
+  VECTORS __VECTOR_BASE FIXED
+  {
+    * (RESET, +FIRST)         ; Vector table and other startup code
+    * (InRoot$$Sections)      ; All (library) code that must be in a root region
+    * (+RO-CODE)              ; Application RO code (.text)
+  }
 
-    VECTORS 0x18004000 FIXED
-    {
-        * (RESET, +FIRST)         ; Vector table and other (assembler) startup code
-        * (InRoot$$Sections)      ; All (library) code that must be in a root region
-        * (+RO-CODE)              ; Application RO code (.text)
-    }
+  RO_DATA    +0
+  { * (+RO-DATA) }              ; Application RO data (.constdata)
 
-    RO_DATA    +0
-    { * (+RO-DATA) }              ; Application RO data (.constdata)
+  RW_DATA 0x20020000
+  { * (+RW) }                   ; Application RW data (.data)
 
-    RW_DATA    0x20020000
-    { * (+RW) }                   ; Application RW data (.data)
+  RW_IRAM1    +0 ALIGN 0x10
+  { * (+ZI) }                   ; Application ZI data (.bss)
 
-    ZI_DATA    +0 ALIGN 0x400
-    { * (+ZI) }                   ; Application ZI data (.bss)
+  ARM_LIB_HEAP  +0
+  { * (HEAP) }                  ; Application heap area (HEAP)
 
-    RW_DATA_NC 0x60900000 0x00100000
-    { * (NC_DATA) }              ; Application RW data Non cached area
+  ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }
 
-    ZI_DATA_NC +0
-    { * (NC_BSS) }               ; Application ZI data Non cached area
-}
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+  ; RAM-NC : Internal non-cached RAM region
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
+  RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE
+  { * (NC_DATA) }              ; Application RW data Non cached area
+
+  ZI_DATA_NC +0
+  { * (NC_BSS) }               ; Application ZI data Non cached area
+}
 

targets/TARGET_RENESAS/TARGET_RZ_A1H/device/TOOLCHAIN_ARM_STD/MBRZA1H.sct

@@ -0,0 +1,77 @@
+/**************************************************************************//**
+ * @file     mem_RZ_A1H.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_RZ_A1H_H
+#define __MEM_RZ_A1H_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __ROM_BASE       0x18000000
+#define __ROM_SIZE       0x08000000
+
+#define __VECTOR_BASE    0x18004000
+
+/*--------------------- RAM Configuration -----------------------------------
+ *----------------------------------------------------------------------------*/
+#define __RAM_BASE       0x20000000
+#define __RAM_SIZE       0x00A00000
+#define __NC_RAM_SIZE    0x00100000
+#define __NM_RAM_SIZE    (__RAM_SIZE - __NC_RAM_SIZE)
+#define __DATA_NC_BASE   (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
+
+#define __UND_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00008000
+#define __ABT_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x0000F000
+#define __STACK_SIZE     (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x20000000
+#define __TTB_SIZE       0x00004000
+
+#endif /* __MEM_RZ_A1H_H */