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brondanibrondani
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Merge branch 'develop' of https://github.com/ARM-software/CMSIS_5 into develop
2 parents 37787f1 + d7783e4 commit c4fa5ee

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‎ARM.CMSIS.pdsc

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,8 @@
1313
CMSIS-Core(A): 1.0.1 (see revision history for details)
1414
- Added compiler_iccarm.h.
1515
- Added additional access functions for physical timer.
16+
Devices:
17+
- Added device ARMCM0plus_MPU for Cortex-M0+ with MPU.
1618
</release>
1719
<release version="5.1.2-dev2">
1820
CMSIS-Core(M): 5.0.3 (see revision history for details)
@@ -250,6 +252,11 @@ The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed
250252
<processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
251253
<compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus.h" define="ARMCM0P"/>
252254
</device>
255+
256+
<device Dname="ARMCM0P_MPU">
257+
<processor Dcore="Cortex-M0+" DcoreVersion="r0p1" Dfpu="NO_FPU" Dmpu="MPU" Dendian="Configurable" Dclock="10000000"/>
258+
<compile header="Device/ARM/ARMCM0plus/Include/ARMCM0plus_MPU.h" define="ARMCM0P_MPU"/>
259+
</device>
253260
</family>
254261

255262
<!-- ****************************** Cortex-M3 ****************************** -->
@@ -1668,7 +1675,7 @@ and 8-bit Java bytecodes in Jazelle state.
16681675

16691676
<condition id="ARMCM0+ CMSIS">
16701677
<description>Generic ARM Cortex-M0+ device startup and depends on CMSIS Core</description>
1671-
<require Dvendor="ARM:82" Dname="ARMCM0P"/>
1678+
<require Dvendor="ARM:82" Dname="ARMCM0P*"/>
16721679
<require Cclass="CMSIS" Cgroup="CORE"/>
16731680
</condition>
16741681
<condition id="ARMCM0+ CMSIS GCC">
@@ -2803,6 +2810,7 @@ and 8-bit Java bytecodes in Jazelle state.
28032810
<description>uVision Simulator</description>
28042811
<mountedDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0"/>
28052812
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P"/>
2813+
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM0P_MPU"/>
28062814
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM3"/>
28072815
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4"/>
28082816
<compatibleDevice deviceIndex="0" Dvendor="ARM:82" Dname="ARMCM4_FP"/>

‎CMSIS/Core/Include/cmsis_iccarm.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -436,6 +436,10 @@ __packed struct __iar_u32 { uint32_t v; };
436436
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
437437
#endif
438438

439+
#ifdef __INTRINSICS_INCLUDED
440+
#error intrinsics.h is already included previously!
441+
#endif
442+
439443
#include <intrinsics.h>
440444

441445
#if __IAR_M0_FAMILY

‎CMSIS/CoreValidation/Include/CV_Typedefs.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -38,9 +38,7 @@ typedef unsigned int BOOL;
3838

3939
#define ARRAY_SIZE(arr) (sizeof(arr)/sizeof((arr)[0]))
4040

41-
#if defined( __GNUC__ )
42-
static const int PATH_DELIMITER = '/';
43-
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
41+
#if defined( __GNUC__ ) || defined ( __clang__ )
4442
static const int PATH_DELIMITER = '/';
4543
#else
4644
static const int PATH_DELIMITER = '\\';

‎CMSIS/CoreValidation/Source/CV_MPU_ARMv7.c

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,6 @@
88
#include "CV_Framework.h"
99
#include "cmsis_cv.h"
1010

11-
#if defined(__MPU_PRESENT) && (__MPU_PRESENT != 0)
12-
1311
/*-----------------------------------------------------------------------------
1412
* Test implementation
1513
*----------------------------------------------------------------------------*/
@@ -115,4 +113,3 @@ void TC_MPU_Load(void)
115113
#undef ASSERT_MPU_REGION
116114
}
117115

118-
#endif

‎CMSIS/CoreValidation/Source/cmsis_cv.c

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -99,11 +99,9 @@ static TEST_CASE TC_LIST[] = {
9999
#endif
100100
#endif
101101
#ifdef RTE_CV_MPUFUNC
102-
#if defined(__MPU_PRESENT) && __MPU_PRESENT
103102
TCD ( TC_MPU_SetClear, TC_MPU_SETCLEAR_EN ),
104103
TCD ( TC_MPU_Load, TC_MPU_LOAD_EN ),
105104
#endif
106-
#endif
107105
#ifdef RTE_CV_GENTIMER
108106
TCD ( TC_GenTimer_CNTFRQ, TC_GENTIMER_CNTFRQ ),
109107
TCD ( TC_GenTimer_CNTP_TVAL, TC_GENTIMER_CNTP_TVAL ),

‎CMSIS/CoreValidation/Tests/ARMCM0plus_config.txt

Lines changed: 24 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,30 @@
11
# Parameters:
22
# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max]
33
#----------------------------------------------------------------------------------------------
4+
armcortexm0plusct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
5+
armcortexm0plusct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
6+
armcortexm0plusct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
7+
armcortexm0plusct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
8+
armcortexm0plusct.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
9+
armcortexm0plusct.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
10+
armcortexm0plusct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
11+
armcortexm0plusct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
12+
armcortexm0plusct.NUM_MPU_REGION=0x8 # (int , init-time) default = '0x0' : Number of MPU regions : [0x0..0x8]
13+
armcortexm0plusct.NUM_IRQ=0x20 # (int , init-time) default = '0x20' : Number of user interrupts : [0x0..0x20]
14+
armcortexm0plusct.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
15+
armcortexm0plusct.min_sync_level=0x0 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
16+
armcortexm0plusct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
17+
armcortexm0plusct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
18+
armcortexm0plusct.master_id=0x0 # (int , init-time) default = '0x0' : Master ID presented in bus transactions : [0x0..0xFFFFFFFF]
19+
armcortexm0plusct.VTOR=1 # (bool , init-time) default = '1' : Include Vector Table Offset Register
20+
armcortexm0plusct.DBG=1 # (bool , init-time) default = '1' : Set whether debug extensions are implemented
21+
armcortexm0plusct.BKPT=0x4 # (int , init-time) default = '0x4' : Number of breakpoint unit comparators implemented : [0x0..0x4]
22+
armcortexm0plusct.WPT=0x2 # (int , init-time) default = '0x2' : Number of watchpoint unit comparators implemented : [0x0..0x2]
23+
armcortexm0plusct.USER=1 # (bool , init-time) default = '1' : Enable support for Unprivileged/Privileged Extension
24+
armcortexm0plusct.SYST=1 # (bool , init-time) default = '1' : Enable support for SysTick timer functionality
25+
armcortexm0plusct.WIC=1 # (bool , init-time) default = '1' : Include support for WIC-mode deep sleep
26+
armcortexm0plusct.IRQDIS=0x0 # (int , init-time) default = '0x0' : IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n] : [0x0..0xFFFFFFFF]
27+
armcortexm0plusct.IOP=0 # (bool , init-time) default = '0' : Send all d-side transactions to the port, io_port_out. Transactions which do not match should be returned to the port, io_port_in
428
fvp_mps2.SCC_ID.Variant=0x0 # (int , init-time) default = '0x0' : SCC_ID[23:20], X in the FGPA version 'rXpY' : [0x0..0xF]
529
fvp_mps2.SCC_ID.Revision=0x1 # (int , init-time) default = '0x1' : SCC_ID[3:0], Y in the FGPA version 'rXpY' : [0x0..0xF]
630
fvp_mps2.iotss_systemcontrol.cpu0wait=0 # (bool , init-time) default = '0' : Whether to hold cpu0 in reset at boot
@@ -217,23 +241,4 @@ fvp_mps2.dma3.fifo_size=0x10 # (int , init-time) defa
217241
fvp_mps2.dma3.max_transfer=0x100 # (int , init-time) default = '0x100' : Largest atomic transfer
218242
fvp_mps2.dma3.generate_clear=0 # (bool , init-time) default = '0' : Generate clear response
219243
fvp_mps2.dma3.activate_delay=0x0 # (int , init-time) default = '0x0' : request delay
220-
armcortexm0ct.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
221-
armcortexm0ct.semihosting-Thumb_SVC=0xAB # (int , init-time) default = '0xAB' : T32 SVC number for semihosting : [0x0..0xFF]
222-
armcortexm0ct.semihosting-cmd_line="" # (string, init-time) default = '' : Command line available to semihosting SVC calls
223-
armcortexm0ct.semihosting-heap_base=0x0 # (int , init-time) default = '0x0' : Virtual address of heap base : [0x0..0xFFFFFFFF]
224-
armcortexm0ct.semihosting-heap_limit=0x0 # (int , init-time) default = '0x10700000' : Virtual address of top of heap : [0x0..0xFFFFFFFF]
225-
armcortexm0ct.semihosting-stack_base=0x0 # (int , init-time) default = '0x10700000' : Virtual address of base of descending stack : [0x0..0xFFFFFFFF]
226-
armcortexm0ct.semihosting-stack_limit=0x0 # (int , init-time) default = '0x10800000' : Virtual address of stack limit : [0x0..0xFFFFFFFF]
227-
armcortexm0ct.semihosting-cwd="" # (string, init-time) default = '' : Base directory for semihosting file access.
228-
armcortexm0ct.NUM_IRQ=0x20 # (int , init-time) default = '0x20' : Number of user interrupts : [0x1..0x20]
229-
armcortexm0ct.BIGENDINIT=0 # (bool , init-time) default = '0' : Initialize processor to big endian mode
230-
armcortexm0ct.min_sync_level=0x0 # (int , run-time ) default = '0x0' : force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll) : [0x0..0x3]
231-
armcortexm0ct.cpi_mul=0x1 # (int , run-time ) default = '0x1' : multiplier for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
232-
armcortexm0ct.cpi_div=0x1 # (int , run-time ) default = '0x1' : divider for calculating CPI (Cycles Per Instruction) : [0x1..0x7FFFFFFF]
233-
armcortexm0ct.master_id=0x0 # (int , init-time) default = '0x0' : Master ID presented in bus transactions : [0x0..0xFFFFFFFF]
234-
armcortexm0ct.DBG=1 # (bool , init-time) default = '1' : Set whether debug extensions are implemented
235-
armcortexm0ct.BKPT=0x4 # (int , init-time) default = '0x4' : Number of breakpoint unit comparators implemented : [0x0..0x4]
236-
armcortexm0ct.WPT=0x2 # (int , init-time) default = '0x2' : Number of watchpoint unit comparators implemented : [0x0..0x2]
237-
armcortexm0ct.SYST=1 # (bool , init-time) default = '1' : Enable support for SysTick timer functionality
238-
armcortexm0ct.WIC=1 # (bool , init-time) default = '1' : Include support for WIC-mode deep sleep
239244
#----------------------------------------------------------------------------------------------

‎CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/CMSIS_CV.uvprojx

Lines changed: 22 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,16 +14,16 @@
1414
<pCCUsed>5060528::V5.06 update 5 (build 528)::ARMCC</pCCUsed>
1515
<TargetOption>
1616
<TargetCommonOption>
17-
<Device>ARMCM0P</Device>
17+
<Device>ARMCM0P_MPU</Device>
1818
<Vendor>ARM</Vendor>
19-
<PackID>ARM.CMSIS.5.1.2-dev1</PackID>
19+
<PackID>ARM.CMSIS.5.1.2-dev3</PackID>
2020
<PackURL>http://www.keil.com/pack/</PackURL>
2121
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0+") CLOCK(12000000) ESEL ELITTLE</Cpu>
2222
<FlashUtilSpec></FlashUtilSpec>
2323
<StartupFile></StartupFile>
2424
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
2525
<DeviceId>0</DeviceId>
26-
<RegisterFile>$$Device:ARMCM0P$Device\ARM\ARMCM0plus\Include\ARMCM0plus.h</RegisterFile>
26+
<RegisterFile>$$Device:ARMCM0P_MPU$Device\ARM\ARMCM0plus\Include\ARMCM0plus_MPU.h</RegisterFile>
2727
<MemoryEnv></MemoryEnv>
2828
<Cmp></Cmp>
2929
<Asm></Asm>
@@ -33,7 +33,7 @@
3333
<SLE66CMisc></SLE66CMisc>
3434
<SLE66AMisc></SLE66AMisc>
3535
<SLE66LinkerMisc></SLE66LinkerMisc>
36-
<SFDFile>$$Device:ARMCM0P$Device\ARM\SVD\ARMCM0P.svd</SFDFile>
36+
<SFDFile>$$Device:ARMCM0P_MPU$Device\ARM\SVD\ARMCM0P.svd</SFDFile>
3737
<bCustSvd>0</bCustSvd>
3838
<UseEnv>0</UseEnv>
3939
<BinPath></BinPath>
@@ -110,11 +110,11 @@
110110
</CommonProperty>
111111
<DllOption>
112112
<SimDllName>SARMCM3.DLL</SimDllName>
113-
<SimDllArguments> </SimDllArguments>
113+
<SimDllArguments> -MPU </SimDllArguments>
114114
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
115115
<SimDlgDllArguments>-pCM0+</SimDlgDllArguments>
116116
<TargetDllName>SARMCM3.DLL</TargetDllName>
117-
<TargetDllArguments> </TargetDllArguments>
117+
<TargetDllArguments>-MPU </TargetDllArguments>
118118
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
119119
<TargetDlgDllArguments>-pCM0+</TargetDlgDllArguments>
120120
</DllOption>
@@ -450,17 +450,29 @@
450450
</components>
451451
<files>
452452
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0plus\Source\ARM\startup_ARMCM0plus.s" version="1.0.0">
453-
<instance index="0">RTE\Device\ARMCM0P\startup_ARMCM0plus.s</instance>
453+
<instance index="0" removed="1">RTE\Device\ARMCM0P\startup_ARMCM0plus.s</instance>
454454
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
455-
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
455+
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
456+
<targetInfos/>
457+
</file>
458+
<file attr="config" category="sourceC" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0">
459+
<instance index="0" removed="1">RTE\Device\ARMCM0P\system_ARMCM0plus.c</instance>
460+
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
461+
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
462+
<targetInfos/>
463+
</file>
464+
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM0plus\Source\ARM\startup_ARMCM0plus.s" version="1.0.0">
465+
<instance index="0">RTE\Device\ARMCM0P_MPU\startup_ARMCM0plus.s</instance>
466+
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
467+
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
456468
<targetInfos>
457469
<targetInfo name="FVP"/>
458470
</targetInfos>
459471
</file>
460472
<file attr="config" category="sourceC" name="Device\ARM\ARMCM0plus\Source\system_ARMCM0plus.c" version="1.0.0">
461-
<instance index="0">RTE\Device\ARMCM0P\system_ARMCM0plus.c</instance>
473+
<instance index="0">RTE\Device\ARMCM0P_MPU\system_ARMCM0plus.c</instance>
462474
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.0.1" condition="ARMCM0+ CMSIS"/>
463-
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev1"/>
475+
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.1.2-dev3"/>
464476
<targetInfos>
465477
<targetInfo name="FVP"/>
466478
</targetInfos>

‎CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/RTE/Device/ARMCM0P/startup_ARMCM0plus.s renamed to ‎CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/RTE/Device/ARMCM0P_MPU/startup_ARMCM0plus.s

File renamed without changes.

‎CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/RTE/Device/ARMCM0P/system_ARMCM0plus.c renamed to ‎CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/RTE/Device/ARMCM0P_MPU/system_ARMCM0plus.c

File renamed without changes.

‎CMSIS/CoreValidation/Tests/Cortex-M0plus/AC5/RTE/_FVP/RTE_Components.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
/*
1515
* Define the Device Header File:
1616
*/
17-
#define CMSIS_device_header "ARMCM0plus.h"
17+
#define CMSIS_device_header "ARMCM0plus_MPU.h"
1818

1919

2020
#endif /* RTE_COMPONENTS_H */

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