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Merge pull request #4740 from jeromecoutant/PR_CONFIG_CLOCK
STM32 : Clock source selection in json config file (PR2)
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‎targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_clock.c

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/* mbed Microcontroller Library
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* Copyright (c) 2006-2017 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* This file configures the system clock as follows:
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*-----------------------------------------------------------------
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* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
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* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
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* | 3- USE_PLL_HSI (internal 8 MHz)
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*-----------------------------------------------------------------
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* SYSCLK(MHz) | 48
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* AHBCLK (MHz) | 48
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* APB1CLK (MHz) | 48
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* USB capable | NO
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*-----------------------------------------------------------------
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*/
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#include "stm32f0xx.h"
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#include "mbed_assert.h"
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#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
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#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board)
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#define USE_PLL_HSI 0x2 // Use HSI internal clock
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#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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uint8_t SetSysClock_PLL_HSI(void);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
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/**
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* @brief Setup the microcontroller system.
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* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001U;
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#if defined (STM32F051x8) || defined (STM32F058x8)
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/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
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RCC->CFGR &= (uint32_t)0xF8FFB80CU;
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#else
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/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
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RCC->CFGR &= (uint32_t)0x08FFB80CU;
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#endif /* STM32F051x8 or STM32F058x8 */
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFFU;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFFU;
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/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
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RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
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/* Reset PREDIV[3:0] bits */
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RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
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#if defined (STM32F072xB) || defined (STM32F078xx)
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/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
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#elif defined (STM32F071xB)
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/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
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#elif defined (STM32F091xC) || defined (STM32F098xx)
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/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
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#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
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/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
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#elif defined (STM32F051x8) || defined (STM32F058xx)
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/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
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#elif defined (STM32F042x6) || defined (STM32F048xx)
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/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
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#elif defined (STM32F070x6) || defined (STM32F070xB)
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/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
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/* Set default USB clock to PLLCLK, since there is no HSI48 */
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RCC->CFGR3 |= (uint32_t)0x00000080U;
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#else
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#warning "No target selected"
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#endif
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/* Reset HSI14 bit */
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RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000U;
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/* Enable SYSCFGENR in APB2EN, needed for 1st call of NVIC_SetVector, to copy vectors from flash to ram */
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RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
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}
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
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* AHB/APBx prescalers and Flash settings
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* @note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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void SetSysClock(void)
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
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/* 1- Try to start with HSE and external clock */
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if (SetSysClock_PLL_HSE(1) == 0)
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#endif
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
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/* 2- If fail try to start with HSE and external xtal */
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if (SetSysClock_PLL_HSE(0) == 0)
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#endif
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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/* 3- If fail start with HSI clock */
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if (SetSysClock_PLL_HSI() == 0)
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#endif
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{
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while(1) {
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MBED_ASSERT(1);
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}
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}
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}
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}
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// Output clock on MCO pin(PA8) for debugging purpose
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//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
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}
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#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
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/******************************************************************************/
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/* PLL (clocked by HSE) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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//Select HSI as system clock source to allow modification of the PLL configuration
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
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if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
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return 0; // FAIL
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}
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// Select HSE oscillator as PLL source
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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if (bypass == 0) {
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RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
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} else {
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
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}
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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// Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
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return 0; // FAIL
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}
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// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
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return 1; // OK
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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/******************************************************************************/
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/* PLL (clocked by HSI) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSI(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct;
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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// Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
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RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.HSI14State = RCC_HSI_OFF;
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RCC_OscInitStruct.HSI14CalibrationValue = RCC_HSI14CALIBRATION_DEFAULT;
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RCC_OscInitStruct.HSI48State = RCC_HSI_ON;
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RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
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RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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// Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
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return 0; // FAIL
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}
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//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
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return 1; // OK
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

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