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Fix bugs for RTL8195AM with debug profile of compilers
1. Add alignment / padding for postbuild segments 2. Clear tcm.bss section 3. Remove TRAP_OverrideTable(), move lines to PLAT_Start()
1 parent a0064ae commit c834b7f

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4 files changed

+34
-26
lines changed

4 files changed

+34
-26
lines changed

targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,8 +56,8 @@ LR_IRAM 0x10007000 (0x70000 - 0x7000) {
5656

5757
LR_TCM 0x1FFF0000 0x10000 {
5858
TCM_OVERLAY 0x1FFF0000 0x10000 {
59-
lwip_mem.o(.bss*)
60-
lwip_memp.o(.bss*)
59+
*lwip_mem.o(.bss*)
60+
*lwip_memp.o(.bss*)
6161
*.o(.tcm.heap*)
6262
}
6363
}

targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,6 @@ SECTIONS
7272
*libc.a: (.text* .rodata*)
7373
*Ticker.o (.text*)
7474
*Timeout.o (.text*)
75-
/* *rtx_timer.o (.text*)*/
7675
*TimerEvent.o (.text*)
7776
*mbed_ticker_api.o (.text*)
7877
*mbed_critical.o (.text*)
@@ -207,7 +206,16 @@ SECTIONS
207206
. = ORIGIN(SRAM1) + LENGTH(SRAM1) - StackSize;
208207
__HeapLimit = .;
209208
} > SRAM1
210-
209+
210+
.TCM_overlay :
211+
{
212+
__bss_dtcm_start__ = .;
213+
*lwip_mem.o (.bss*)
214+
*lwip_memp.o (.bss*)
215+
*(.tcm.heap*)
216+
__bss_dtcm_end__ = .;
217+
} > TCM
218+
211219
/* .stack_dummy section doesn't contains any symbols. It is only
212220
* used for linker to calculate size of stack sections, and assign
213221
* values to stack symbols later */

targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c

Lines changed: 18 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -30,12 +30,17 @@
3030
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
3131
extern uint8_t Image$$RW_IRAM2$$ZI$$Base[];
3232
extern uint8_t Image$$RW_IRAM2$$ZI$$Limit[];
33+
extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[];
34+
extern uint8_t Image$$TCM_OVERLAY$$ZI$$Limit[];
3335
extern uint8_t Image$$RW_DRAM2$$ZI$$Base[];
3436
extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[];
3537
#define __bss_sram_start__ Image$$RW_IRAM2$$ZI$$Base
3638
#define __bss_sram_end__ Image$$RW_IRAM2$$ZI$$Limit
39+
#define __bss_dtcm_start__ Image$$TCM_OVERLAY$$ZI$$Base
40+
#define __bss_dtcm_end__ Image$$TCM_OVERLAY$$ZI$$Limit
3741
#define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base
3842
#define __bss_dram_end__ Image$$RW_DRAM2$$ZI$$Limit
43+
#define __stackp Image$$ARM_LIB_STACK$$ZI$$Limit
3944

4045
#elif defined (__ICCARM__)
4146

@@ -50,15 +55,20 @@ void __iar_data_init_app(void)
5055
__bss_start__ = (uint8_t *)__section_begin(".ram.bss");
5156
__bss_end__ = (uint8_t *)__section_end(".ram.bss");
5257
}
58+
#define __stackp CSTACK$$Limit
5359

5460
#else
5561

5662
extern uint32_t __StackTop;
63+
extern uint32_t __StackLimit;
5764
extern uint8_t __bss_sram_start__[];
5865
extern uint8_t __bss_sram_end__[];
66+
extern uint8_t __bss_dtcm_start__[];
67+
extern uint8_t __bss_dtcm_end__[];
5968
extern uint8_t __bss_dram_start__[];
6069
extern uint8_t __bss_dram_end__[];
6170

71+
#define __stackp __StackTop
6272
#endif
6373

6474
extern VECTOR_Func NewVectorTable[];
@@ -161,20 +171,6 @@ void TRAP_HardFaultHandler_Patch(void)
161171
}
162172
#endif
163173

164-
// Override original Interrupt Vector Table
165-
void TRAP_OverrideTable(uint32_t stackp)
166-
{
167-
// Set MSP
168-
__set_MSP(stackp);
169-
170-
// Override NMI Handler
171-
NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
172-
173-
#if defined ( __ICCARM__ )
174-
NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
175-
#endif
176-
}
177-
178174
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
179175
// Image2 Entry Function
180176
void PLAT_Start(void)
@@ -190,18 +186,18 @@ void PLAT_Start(void)
190186
__rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
191187
#else
192188
__rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
189+
__rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__);
193190
__rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
194191
#endif
195192

196-
#if defined (__CC_ARM)
197-
TRAP_OverrideTable((uint32_t)&Image$$ARM_LIB_STACK$$ZI$$Limit);
198-
#elif defined (__ICCARM__)
199-
TRAP_OverrideTable((uint32_t)&CSTACK$$Limit);
200-
#elif defined (__GNUC__)
201-
TRAP_OverrideTable((uint32_t)&__StackTop);
202-
#else
203-
TRAP_OverrideTable(0x1FFFFFFC);
193+
// Set MSP
194+
__set_MSP((uint32_t)&__stackp - 0x100);
195+
// Overwrite vector table
196+
NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
197+
#if defined ( __ICCARM__ )
198+
NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
204199
#endif
200+
205201
extern HAL_TIMER_OP_EXT HalTimerOpExt;
206202
__rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
207203
__rtl_memset_v1_00((void *)&HalTimerOp, 0, sizeof(HalTimerOp));

tools/targets/REALTEK_RTL8195AM.py

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -240,6 +240,10 @@ def write_load_segment(image_elf, image_bin, segment):
240240
write_fixed_width_value(size, 8, file_bin)
241241
# write load segment
242242
file_bin.write(file_elf.read(size))
243+
delta = size % 4
244+
if delta != 0:
245+
padding = 4 - delta
246+
write_fixed_width_value(0x0, padding * 2, file_bin)
243247
file_bin.close()
244248
file_elf.close()
245249

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