Merge pull request #144 from 0xc0170/dev_k20d5m_testing

K20D50M target - pwm and clocks in HAL

Author: bogdanm

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/analogin_api.c

@@ -18,6 +18,7 @@
 #include "cmsis.h"
 #include "pinmap.h"
 #include "error.h"
+#include "clk_freqs.h"
 
 static const PinMap PinMap_ADC[] = {
     {PTC2, ADC0_SE4b, 0},
@@ -33,6 +34,8 @@ static const PinMap PinMap_ADC[] = {
     {NC,   NC,        0}
 };
 
+#define MAX_FADC        6000000
+
 void analogin_init(analogin_t *obj, PinName pin) {
     obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
     if (obj->adc == (ADCName)NC)
@@ -43,13 +46,23 @@ void analogin_init(analogin_t *obj, PinName pin) {
     uint32_t port = (uint32_t)pin >> PORT_SHIFT;
     SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
 
+    // bus clk
+    uint32_t PCLK = bus_frequency();
+    uint32_t clkdiv;
+    for (clkdiv = 0; clkdiv < 4; clkdiv++) {
+        if ((PCLK >> clkdiv) <= MAX_FADC)
+            break;
+    }
+    if (clkdiv == 4)                    //Set max div
+        clkdiv = 0x7;
+
     ADC0->SC1[1] = ADC_SC1_ADCH(obj->adc);
 
     ADC0->CFG1 = ADC_CFG1_ADLPC_MASK    // Low-Power Configuration
-               | ADC_CFG1_ADIV(3)       // Clock Divide Select: (Input Clock)/8
+               | ADC_CFG1_ADIV(clkdiv & 0x3)       // Clock Divide Select
                | ADC_CFG1_ADLSMP_MASK   // Long Sample Time
                | ADC_CFG1_MODE(3)       // (16)bits Resolution
-               | ADC_CFG1_ADICLK(1);    // Input Clock: (Bus Clock)/2
+               | ADC_CFG1_ADICLK(clkdiv >> 2);    // Input Clock
 
     ADC0->CFG2 = ADC_CFG2_MUXSEL_MASK   // ADxxb or ADxxa channels
                | ADC_CFG2_ADACKEN_MASK  // Asynchronous Clock Output Enable

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/clk_freqs.h

@@ -0,0 +1,97 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef CLK_FREQS_H
+#define CLK_FREQS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * \brief Get the peripheral bus clock frequency
+ * \return Bus frequency
+ */
+static inline uint32_t bus_frequency(void) {
+    return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
+}
+
+/*!
+ * \brief Get external oscillator (crystal) frequency
+ * \return External osc frequency
+ */
+static uint32_t extosc_frequency(void) {
+    uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
+
+    if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2))     //MCG clock = external reference clock
+        return MCGClock;
+
+    if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) {   //PLL/FLL is selected
+        uint32_t divider, multiplier;
+        if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {         //FLL is selected
+            if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) {     //FLL uses external reference
+                divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+                if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
+                    divider <<= 5u;
+                /* Select correct multiplier to calculate the MCG output clock  */
+                switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+                    case 0x0u:
+                      multiplier = 640u;
+                      break;
+                    case 0x20u:
+                      multiplier = 1280u;
+                      break;
+                    case 0x40u:
+                      multiplier = 1920u;
+                      break;
+                    case 0x60u:
+                      multiplier = 2560u;
+                      break;
+                    case 0x80u:
+                      multiplier = 732u;
+                      break;
+                    case 0xA0u:
+                      multiplier = 1464u;
+                      break;
+                    case 0xC0u:
+                      multiplier = 2197u;
+                      break;
+                    case 0xE0u:
+                    default:
+                      multiplier = 2929u;
+                      break;
+                }
+
+                return MCGClock * divider / multiplier;
+            }
+        } else {             //PLL is selected
+            divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+            multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+            return MCGClock * divider / multiplier;
+        }
+    }
+
+    //In all other cases either there is no crystal or we cannot determine it
+    //For example when the FLL is running on the internal reference, and there is also an
+    //external crystal. However these are unlikely situations
+    return 0;
+}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/i2c_api.c

@@ -18,6 +18,7 @@
 #include "cmsis.h"
 #include "pinmap.h"
 #include "error.h"
+#include "clk_freqs.h"
 
 static const PinMap PinMap_I2C_SDA[] = {
     {PTB1,  I2C_0, 2},
@@ -165,10 +166,11 @@ static int i2c_do_write(i2c_t *obj, int value) {
 }
 
 static int i2c_do_read(i2c_t *obj, char * data, int last) {
-    if (last)
+    if (last) {
         i2c_send_nack(obj);
-    else
+    } else {
         i2c_send_ack(obj);
+    }
 
     *data = (obj->i2c->D & 0xFF);
 
@@ -184,7 +186,7 @@ void i2c_frequency(i2c_t *obj, int hz) {
     uint32_t ref = 0;
     uint8_t i, j;
     // bus clk
-    uint32_t PCLK = 24000000u;
+    uint32_t PCLK = bus_frequency();
     uint32_t pulse = PCLK / (hz * 2);
 
     // we look for the values that minimize the error
@@ -237,9 +239,8 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
     }
 
     // If not repeated start, send stop.
-    if (stop) {
+    if (stop)
         i2c_stop(obj);
-    }
 
     // last read
     data[count-1] = obj->i2c->D;
@@ -326,11 +327,9 @@ int i2c_slave_receive(i2c_t *obj) {
         // read addressed
         case 0xE6:
             return 1;
-
         // write addressed
         case 0xE2:
             return 3;
-
         default:
             return 0;
     }

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/objects.h

@@ -43,7 +43,6 @@ struct pwmout_s {
     __IO uint32_t *MOD;
     __IO uint32_t *CNT;
     __IO uint32_t *CnV;
-    __IO uint32_t *SYNC;
 };
 
 struct serial_s {

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/pwmout_api.c

@@ -21,28 +21,52 @@
 
 static const PinMap PinMap_PWM[] = {
     // LEDs
-    {LED_RED  , PWM_3 , 3}, // PTC3, FTM0 CH2
-    {LED_GREEN, PWM_5, 3},  // PTD4, FTM0 CH4
-    {LED_BLUE , PWM_9 , 3}, // PTA2 , FTM0 CH7
+    {LED_RED  , PWM_3 , 4}, // PTC3, FTM0 CH2
+    {LED_GREEN, PWM_5,  4}, // PTD4, FTM0 CH4
+    {LED_BLUE , PWM_8 , 3}, // PTA2, FTM0 CH7
 
     // Arduino digital pinout
-    {D3,  PWM_5 , 3}, // PTD4, FTM0 CH4
-    {D5,  PWM_7 , 3}, // PTA1 , FTM0 CH6
-    {D6,  PWM_3 , 3}, // PTC3 , FTM0 CH2
-    {D9,  PWM_8 , 4}, // PTD2 , FTM0 CH7
-    {D10, PWM_2 , 4}, // PTC2 , FTM0 CH1
+    {D3,  PWM_5 , 4}, // PTD4, FTM0 CH4
+    {D5,  PWM_7 , 3}, // PTA1, FTM0 CH6
+    {D6,  PWM_3 , 4}, // PTC3, FTM0 CH2
+    {D9,  PWM_6 , 4}, // PTD5, FTM0 CH6
+    {D10, PWM_2 , 4}, // PTC2, FTM0 CH1
+
+    {PTA0,  PWM_6 , 3}, // PTA0, FTM0 CH5
+    {PTA3,  PWM_1 , 3}, // PTA3, FTM0 CH0
+    {PTA4,  PWM_2 , 3}, // PTA4, FTM0 CH1
+    {PTA5,  PWM_3 , 3}, // PTA5, FTM0 CH2
+    {PTA12, PWM_9 , 3}, // PTA12, FTM1 CH0
+    {PTA13, PWM_10, 3}, // PTA13, FTM1 CH1
+    {PTB0,  PWM_9 , 3}, // PTB0, FTM1 CH0
+    {PTB1,  PWM_10, 3}, // PTB1, FTM1 CH1
+    {PTC1,  PWM_1 , 4}, // PTC1, FTM0 CH0
+    {PTD4,  PWM_4 , 4}, // PTD4, FTM0 CH3
+    {PTD6,  PWM_7 , 4}, // PTD6, FTM0 CH6
+    {PTD7,  PWM_8 , 4}, // PTD7, FTM0 CH7
 
     {NC , NC    , 0}
 };
 
-#define PWM_CLOCK_MHZ       (0.75) // (48)MHz / 64 = (0.75)MHz
+static float pwm_clock = 0;
 
 void pwmout_init(pwmout_t* obj, PinName pin) {
     // determine the channel
     PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
     if (pwm == (PWMName)NC)
         error("PwmOut pin mapping failed");
 
+    uint32_t clkdiv = 0;
+    float clkval = SystemCoreClock / 1000000.0f;
+
+    while (clkval > 1) {
+        clkdiv++;
+        clkval /= 2.0;
+        if (clkdiv == 7)
+            break;
+    }
+
+    pwm_clock = clkval;
     unsigned int port = (unsigned int)pin >> PORT_SHIFT;
     unsigned int ftm_n = (pwm >> TPM_SHIFT);
     unsigned int ch_n = (pwm & 0xFF);
@@ -51,22 +75,17 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
     SIM->SCGC6 |= 1 << (SIM_SCGC6_FTM0_SHIFT + ftm_n);
 
     FTM_Type *ftm = (FTM_Type *)(FTM0_BASE + 0x1000 * ftm_n);
-    ftm->MODE |= FTM_MODE_WPDIS_MASK; //write protection disabled
     ftm->CONF |= FTM_CONF_BDMMODE(3);
-    ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(6); // (48)MHz / 64 = (0.75)MHz
+    ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(clkdiv); // (clock)MHz / clkdiv ~= (0.75)MHz
     ftm->CONTROLS[ch_n].CnSC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); /* No Interrupts; High True pulses on Edge Aligned PWM */
-    ftm->PWMLOAD |= FTM_PWMLOAD_LDOK_MASK; //loading updated values enabled
-    //ftm->SYNCONF |= FTM_SYNCONF_SWRSTCNT_MASK;
-    ftm->MODE |= FTM_MODE_INIT_MASK;
 
     obj->CnV = &ftm->CONTROLS[ch_n].CnV;
     obj->MOD = &ftm->MOD;
     obj->CNT = &ftm->CNT;
-    obj->SYNC = &ftm->SYNC;
 
     // default to 20ms: standard for servos, and fine for e.g. brightness control
     pwmout_period_ms(obj, 20);
-    pwmout_write    (obj, 0);
+    pwmout_write(obj, 0);
 
     // Wire pinout
     pinmap_pinout(pin, PinMap_PWM);
@@ -82,8 +101,6 @@ void pwmout_write(pwmout_t* obj, float value) {
     }
 
     *obj->CnV = (uint32_t)((float)(*obj->MOD) * value);
-    *obj->CNT = 0;
-    //*obj->SYNC |= FTM_SYNC_SWSYNC_MASK;
 }
 
 float pwmout_read(pwmout_t* obj) {
@@ -102,7 +119,7 @@ void pwmout_period_ms(pwmout_t* obj, int ms) {
 // Set the PWM period, keeping the duty cycle the same.
 void pwmout_period_us(pwmout_t* obj, int us) {
     float dc = pwmout_read(obj);
-    *obj->MOD = PWM_CLOCK_MHZ * us;
+    *obj->MOD = (uint32_t)(pwm_clock * (float)us);
     pwmout_write(obj, dc);
 }
 
@@ -115,5 +132,5 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
 }
 
 void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
-    *obj->CnV = PWM_CLOCK_MHZ * us;
+    *obj->CnV = (uint32_t)(pwm_clock * (float)us);
 }

libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/serial_api.c

@@ -53,7 +53,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
     obj->uart = (UART_Type *)uart;
     // enable clk
     switch (uart) {
-        case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK | (1<<SIM_SOPT5_UART0TXSRC_SHIFT);
+        case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;
                      SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; break;
         case UART_1: SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break;
         case UART_2: SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK; SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break;
@@ -98,8 +98,7 @@ void serial_baud(serial_t *obj, int baudrate) {
     // Disable UART before changing registers
     obj->uart->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
 
-    // [TODO] not hardcode this value
-    uint32_t PCLK = (obj->uart == UART0) ? 48000000u : 24000000u;
+    uint32_t PCLK = (obj->uart == UART0) ? SystemCoreClock : SystemCoreClock/2;
 
     // First we check to see if the basic divide with no DivAddVal/MulVal
     // ratio gives us an integer result. If it does, we set DivAddVal = 0,