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Merge pull request #881 from Willem23/master
I2CSlave support for lpc812
2 parents be04314 + 3aff0e7 commit cef6954

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3 files changed

+274
-21
lines changed

3 files changed

+274
-21
lines changed

‎libraries/mbed/hal/i2c_api.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,8 @@ void i2c_slave_mode (i2c_t *obj, int enable_slave);
4646
int i2c_slave_receive(i2c_t *obj);
4747
int i2c_slave_read (i2c_t *obj, char *data, int length);
4848
int i2c_slave_write (i2c_t *obj, const char *data, int length);
49+
int i2c_slave_byte_read(i2c_t *obj, int last);
50+
int i2c_slave_byte_write(i2c_t *obj, int data);
4951
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
5052
#endif
5153

‎libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC810/system_LPC8xx.c

Lines changed: 23 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -100,14 +100,18 @@
100100
// </h>
101101
// </e>
102102
*/
103+
104+
// 1 == IRC 12Mhz 2 == System Oscillator 12Mhz Xtal:
103105
#define CLOCK_SETUP 1
106+
//use PLL for IRC
104107
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
105108
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
106-
#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
107-
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
108-
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
109-
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
110-
109+
#define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 MSEL=1 => M=2; PSEL=2 => 2P=8; PLLCLKOUT = (12x2) = 24MHz
110+
//#define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
111+
#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC
112+
#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT
113+
#define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 DIV=1 => SYSTEMCORECLK = 24 / 1 = 24MHz
114+
//#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
111115
/*
112116
//-------- <<< end of configuration section >>> ------------------------------
113117
*/
@@ -235,9 +239,10 @@
235239
/*----------------------------------------------------------------------------
236240
Clock Variable definitions
237241
*----------------------------------------------------------------------------*/
238-
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
239-
242+
uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
243+
uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
240244

245+
//Replaced SystemCoreClock with MainClock
241246
/*----------------------------------------------------------------------------
242247
Clock functions
243248
*----------------------------------------------------------------------------*/
@@ -268,46 +273,46 @@ void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
268273

269274
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
270275
case 0: /* Internal RC oscillator */
271-
SystemCoreClock = __IRC_OSC_CLK;
276+
MainClock = __IRC_OSC_CLK;
272277
break;
273278
case 1: /* Input Clock to System PLL */
274279
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
275280
case 0: /* Internal RC oscillator */
276-
SystemCoreClock = __IRC_OSC_CLK;
281+
MainClock = __IRC_OSC_CLK;
277282
break;
278283
case 1: /* System oscillator */
279-
SystemCoreClock = __SYS_OSC_CLK;
284+
MainClock = __SYS_OSC_CLK;
280285
break;
281286
case 2: /* Reserved */
282-
SystemCoreClock = 0;
287+
MainClock = 0;
283288
break;
284289
case 3: /* CLKIN pin */
285-
SystemCoreClock = __CLKIN_CLK;
290+
MainClock = __CLKIN_CLK;
286291
break;
287292
}
288293
break;
289294
case 2: /* WDT Oscillator */
290-
SystemCoreClock = wdt_osc;
295+
MainClock = wdt_osc;
291296
break;
292297
case 3: /* System PLL Clock Out */
293298
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
294299
case 0: /* Internal RC oscillator */
295-
SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
300+
MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
296301
break;
297302
case 1: /* System oscillator */
298-
SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
303+
MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
299304
break;
300305
case 2: /* Reserved */
301-
SystemCoreClock = 0;
306+
MainClock = 0;
302307
break;
303308
case 3: /* CLKIN pin */
304-
SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
309+
MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
305310
break;
306311
}
307312
break;
308313
}
309314

310-
SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
315+
SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
311316

312317
}
313318

‎libraries/mbed/targets/hal/TARGET_NXP/TARGET_LPC81X/i2c_api.c

Lines changed: 249 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,8 @@
1717
#include "cmsis.h"
1818
#include "pinmap.h"
1919

20+
#if DEVICE_I2C
21+
2022
static const SWM_Map SWM_I2C_SDA[] = {
2123
{7, 24},
2224
};
@@ -75,6 +77,10 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
7577
i2c_interface_enable(obj);
7678
}
7779

80+
//Actually Wrong. Spec says: First store Address in DAT before setting STA !
81+
//Undefined state when using single byte I2C operations and too much delay
82+
//between i2c_start and do_i2c_write(Address).
83+
//Also note that lpc812 will immediately continue reading a byte when Address b0 == 1
7884
inline int i2c_start(i2c_t *obj) {
7985
int status = 0;
8086
if (repeated_start) {
@@ -86,16 +92,15 @@ inline int i2c_start(i2c_t *obj) {
8692
return status;
8793
}
8894

89-
90-
9195
//Generate Stop condition and wait until bus is Idle
9296
//Will also send NAK for previous RD
9397
inline int i2c_stop(i2c_t *obj) {
9498
int timeout = 0;
9599

96100
obj->i2c->MSTCTL = (1 << 2) | (1 << 0); // STP bit and Continue bit. Sends NAK to complete previous RD
97101

98-
while ((obj->i2c->STAT & ((7 << 1) | (1 << 0))) != ((0 << 1) | (1 << 0))) { //Spin until Ready (b0 == 1)and Status is Idle (b3..b1 == 000)
102+
//Spin until Ready (b0 == 1)and Status is Idle (b3..b1 == 000)
103+
while ((obj->i2c->STAT & ((7 << 1) | (1 << 0))) != ((0 << 1) | (1 << 0))) {
99104
timeout ++;
100105
if (timeout > 100000) return 1;
101106
}
@@ -265,3 +270,244 @@ int i2c_byte_write(i2c_t *obj, int data) {
265270

266271
return ack;
267272
}
273+
274+
#if DEVICE_I2CSLAVE
275+
276+
#define I2C_SLVDAT(x) (x->i2c->SLVDAT)
277+
#define I2C_SLVSTAT(x) ((x->i2c->STAT >> 9) & (0x03))
278+
#define I2C_SLVSI(x) ((x->i2c->STAT >> 8) & (0x01))
279+
//#define I2C_SLVCNT(x) (x->i2c->SLVCTL = (1 << 0))
280+
//#define I2C_SLVNAK(x) (x->i2c->SLVCTL = (1 << 1))
281+
282+
#if(0)
283+
// Wait until the Slave Serial Interrupt (SI) is set
284+
// Timeout when it takes too long.
285+
static int i2c_wait_slave_SI(i2c_t *obj) {
286+
int timeout = 0;
287+
while (!(obj->i2c->STAT & (1 << 8))) {
288+
timeout++;
289+
if (timeout > 100000) return -1;
290+
}
291+
return 0;
292+
}
293+
#endif
294+
295+
void i2c_slave_mode(i2c_t *obj, int enable_slave) {
296+
297+
if (enable_slave) {
298+
// obj->i2c->CFG &= ~(1 << 0); //Disable Master mode
299+
obj->i2c->CFG |= (1 << 1); //Enable Slave mode
300+
}
301+
else {
302+
// obj->i2c->CFG |= (1 << 0); //Enable Master mode
303+
obj->i2c->CFG &= ~(1 << 1); //Disable Slave mode
304+
}
305+
}
306+
307+
// Wait for next I2C event and find out what is going on
308+
//
309+
int i2c_slave_receive(i2c_t *obj) {
310+
int addr;
311+
312+
// Check if there is any data pending
313+
if (! I2C_SLVSI(obj)) {
314+
return 0; //NoData
315+
};
316+
317+
// Check State
318+
switch(I2C_SLVSTAT(obj)) {
319+
case 0x0: // Slave address plus R/W received
320+
// At least one of the four slave addresses has been matched by hardware.
321+
// You can figure out which address by checking Slave address match Index in STAT register.
322+
323+
// Get the received address
324+
addr = I2C_SLVDAT(obj) & 0xFF;
325+
// Send ACK on address and Continue
326+
obj->i2c->SLVCTL = (1 << 0);
327+
328+
if (addr == 0x00) {
329+
return 2; //WriteGeneral
330+
}
331+
//check the RW bit
332+
if ((addr & 0x01) == 0x01) {
333+
return 1; //ReadAddressed
334+
}
335+
else {
336+
return 3; //WriteAddressed
337+
}
338+
//break;
339+
340+
case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
341+
// Oops, should never get here...
342+
obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data, try to recover...
343+
return 0; //NoData
344+
345+
case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
346+
// Oops, should never get here...
347+
I2C_SLVDAT(obj) = 0xFF; // Send dummy data for transmission
348+
obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover...
349+
return 0; //NoData
350+
351+
case 0x3: // Reserved.
352+
default: // Oops, should never get here...
353+
obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover...
354+
return 0; //NoData
355+
//break;
356+
} //switch status
357+
}
358+
359+
// The dedicated I2C Slave byte read and byte write functions need to be called
360+
// from 'common' mbed I2CSlave API for devices that have separate Master and
361+
// Slave engines such as the lpc812 and lpc1549.
362+
363+
//Called when Slave is addressed for Write, Slave will receive Data in polling mode
364+
//Parameter last=1 means received byte will be NACKed.
365+
int i2c_slave_byte_read(i2c_t *obj, int last) {
366+
int data;
367+
368+
// Wait for data
369+
while (!I2C_SLVSI(obj)); // Wait forever
370+
//if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
371+
372+
// Dont bother to check State, were not returning it anyhow..
373+
//if (I2C_SLVSTAT(obj)) == 0x01) {
374+
// Slave receive. Received data is available (Slave Receiver mode).
375+
//};
376+
377+
data = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data
378+
if (last) {
379+
obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data and Continue
380+
}
381+
else {
382+
obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read
383+
}
384+
385+
return data;
386+
}
387+
388+
389+
//Called when Slave is addressed for Read, Slave will send Data in polling mode
390+
//
391+
int i2c_slave_byte_write(i2c_t *obj, int data) {
392+
393+
// Wait until Ready
394+
while (!I2C_SLVSI(obj)); // Wait forever
395+
// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
396+
397+
// Check State
398+
switch(I2C_SLVSTAT(obj)) {
399+
case 0x0: // Slave address plus R/W received
400+
// At least one of the four slave addresses has been matched by hardware.
401+
// You can figure out which address by checking Slave address match Index in STAT register.
402+
// I2C Restart occurred
403+
return -1;
404+
//break;
405+
case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
406+
// Should not get here...
407+
return -2;
408+
//break;
409+
case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
410+
I2C_SLVDAT(obj) = data & 0xFF; // Store the data for transmission
411+
obj->i2c->SLVCTL = (1 << 0); // Continue to send
412+
413+
return 1;
414+
//break;
415+
case 0x3: // Reserved.
416+
default:
417+
// Should not get here...
418+
return -3;
419+
//break;
420+
} // switch status
421+
}
422+
423+
424+
//Called when Slave is addressed for Write, Slave will receive Data in polling mode
425+
//Parameter length (>=1) is the maximum allowable number of bytes. All bytes will be ACKed.
426+
int i2c_slave_read(i2c_t *obj, char *data, int length) {
427+
int count=0;
428+
429+
// Read and ACK all expected bytes
430+
while (count < length) {
431+
// Wait for data
432+
while (!I2C_SLVSI(obj)); // Wait forever
433+
// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
434+
435+
// Check State
436+
switch(I2C_SLVSTAT(obj)) {
437+
case 0x0: // Slave address plus R/W received
438+
// At least one of the four slave addresses has been matched by hardware.
439+
// You can figure out which address by checking Slave address match Index in STAT register.
440+
// I2C Restart occurred
441+
return -1;
442+
//break;
443+
444+
case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
445+
data[count] = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data
446+
obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read
447+
break;
448+
449+
case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
450+
case 0x3: // Reserved.
451+
default: // Should never get here...
452+
return -2;
453+
//break;
454+
} // switch status
455+
456+
count++;
457+
} // for all bytes
458+
459+
return count; // Received the expected number of bytes
460+
}
461+
462+
463+
//Called when Slave is addressed for Read, Slave will send Data in polling mode
464+
//Parameter length (>=1) is the maximum number of bytes. Exit when Slave byte is NACKed.
465+
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
466+
int count;
467+
468+
// Send and all bytes or Exit on NAK
469+
for (count=0; count < length; count++) {
470+
// Wait until Ready for data
471+
while (!I2C_SLVSI(obj)); // Wait forever
472+
// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout
473+
474+
// Check State
475+
switch(I2C_SLVSTAT(obj)) {
476+
case 0x0: // Slave address plus R/W received
477+
// At least one of the four slave addresses has been matched by hardware.
478+
// You can figure out which address by checking Slave address match Index in STAT register.
479+
// I2C Restart occurred
480+
return -1;
481+
//break;
482+
case 0x1: // Slave receive. Received data is available (Slave Receiver mode).
483+
// Should not get here...
484+
return -2;
485+
//break;
486+
case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode).
487+
I2C_SLVDAT(obj) = data[count] & 0xFF; // Store the data for transmission
488+
obj->i2c->SLVCTL = (1 << 0); // Continue to send
489+
break;
490+
case 0x3: // Reserved.
491+
default:
492+
// Should not get here...
493+
return -3;
494+
//break;
495+
} // switch status
496+
} // for all bytes
497+
498+
return length; // Transmitted the max number of bytes
499+
}
500+
501+
502+
// Set the four slave addresses.
503+
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
504+
obj->i2c->SLVADR0 = (address & 0xFE); // Store address in address 0 register
505+
obj->i2c->SLVADR1 = (0x00 & 0xFE); // Store general call write address in address 1 register
506+
obj->i2c->SLVADR2 = (0x01); // Disable address 2 register
507+
obj->i2c->SLVADR3 = (0x01); // Disable address 3 register
508+
obj->i2c->SLVQUAL0 = (mask & 0xFE); // Qualifier mask for address 0 register. Any maskbit that is 1 will always be a match
509+
}
510+
511+
#endif
512+
513+
#endif

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