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‎features/nanostack/nanostack-interface/targets/TARGET_Freescale/TARGET_KW41Z/NanostackRfPhyKw41z.cpp

Lines changed: 92 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -68,9 +68,9 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
6868
static void rf_mac_hw_init(void);
6969
static void rf_mac_ed_state_enable(void);
7070
static void rf_mac_set_pending(uint8_t status);
71-
static void rf_mac_set_shortAddress(uint8_t* valueAddress);
72-
static void rf_mac_set_panId(uint8_t* valueAddress);
73-
static void rf_mac_set_mac64(const uint8_t* valueAddress);
71+
static void rf_mac_set_shortAddress(uint8_t *valueAddress);
72+
static void rf_mac_set_panId(uint8_t *valueAddress);
73+
static void rf_mac_set_mac64(const uint8_t *valueAddress);
7474
static uint8_t rf_convert_energy_level(uint8_t energyLevel);
7575
static void rf_abort(void);
7676
static void rf_ack_wait_timer_start(uint16_t time);
@@ -100,16 +100,16 @@ static uint8_t PHYPAYLOAD[MAC_PACKET_SIZE];
100100
const phy_rf_channel_configuration_s phy_2_4ghz = {2405000000U, 5000000U, 250000U, 16U, M_OQPSK};
101101

102102
const phy_device_channel_page_s phy_channel_pages[] = {
103-
{CHANNEL_PAGE_0, &phy_2_4ghz},
104-
{CHANNEL_PAGE_0, NULL}
103+
{CHANNEL_PAGE_0, &phy_2_4ghz},
104+
{CHANNEL_PAGE_0, NULL}
105105
};
106106

107107
static phy_device_driver_s device_driver = {
108108
PHY_LINK_15_4_2_4GHZ_TYPE,
109109
PHY_LAYER_PAYLOAD_DATA_FLOW,
110110
MAC64_addr,
111111
PHY_MTU_SIZE,
112-
(char*)"NXP kw41z",
112+
(char *)"NXP kw41z",
113113
CRC_LENGTH,
114114
PHY_HEADER_LENGTH,
115115
&rf_interface_state_control,
@@ -184,9 +184,9 @@ static void rf_promiscuous(uint8_t state)
184184
/* FRM_VER[11:8] = b0011. Accept FrameVersion 0 and 1 packets, reject all others */
185185
/* Beacon, Data and MAC command frame types accepted */
186186
ZLL->RX_FRAME_FILTER &= ~(ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK |
187-
ZLL_RX_FRAME_FILTER_ACK_FT_MASK |
188-
ZLL_RX_FRAME_FILTER_NS_FT_MASK |
189-
ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK);
187+
ZLL_RX_FRAME_FILTER_ACK_FT_MASK |
188+
ZLL_RX_FRAME_FILTER_NS_FT_MASK |
189+
ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK);
190190
ZLL->RX_FRAME_FILTER |= ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(3);
191191
}
192192
}
@@ -211,8 +211,7 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_
211211
{
212212
platform_enter_critical();
213213

214-
switch (new_state)
215-
{
214+
switch (new_state) {
216215
/*Reset PHY driver and set to idle*/
217216
case PHY_INTERFACE_RESET:
218217
rf_abort();
@@ -294,7 +293,7 @@ static void rf_abort(void)
294293
if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_TMRTRIGEN_MASK) {
295294
ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_TMRTRIGEN_MASK;
296295
/* give the FSM enough time to start if it was triggered */
297-
while( (XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) == 0) {}
296+
while ((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) == 0) {}
298297
}
299298

300299
/* If XCVR is not idle, abort current SEQ */
@@ -347,7 +346,7 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
347346
need_ack = (*data_ptr & 0x20) == 0x20;
348347

349348
/* Load data into Packet Buffer */
350-
pPB = (uint8_t*)ZLL->PKT_BUFFER_TX;
349+
pPB = (uint8_t *)ZLL->PKT_BUFFER_TX;
351350

352351
tx_len = data_length + 2;
353352
*pPB++ = tx_len; /* including 2 bytes of FCS */
@@ -382,7 +381,7 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
382381
ZLL->IRQSTS = irqSts;
383382

384383
tx_warmup_time = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >>
385-
XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT;
384+
XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT;
386385

387386
/* Compute warmup times (scaled to 16us) */
388387
if (tx_warmup_time & 0x0F) {
@@ -418,19 +417,19 @@ static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address
418417
platform_enter_critical();
419418

420419
switch (address_type) {
421-
case PHY_MAC_64BIT:
422-
rf_mac_set_mac64(address_ptr);
423-
break;
424-
/*Set 16-bit address*/
425-
case PHY_MAC_16BIT:
426-
rf_mac_set_shortAddress(address_ptr);
427-
break;
428-
/*Set PAN Id*/
429-
case PHY_MAC_PANID:
430-
rf_mac_set_panId(address_ptr);
431-
break;
432-
default:
433-
ret_val = -1;
420+
case PHY_MAC_64BIT:
421+
rf_mac_set_mac64(address_ptr);
422+
break;
423+
/*Set 16-bit address*/
424+
case PHY_MAC_16BIT:
425+
rf_mac_set_shortAddress(address_ptr);
426+
break;
427+
/*Set PAN Id*/
428+
case PHY_MAC_PANID:
429+
rf_mac_set_panId(address_ptr);
430+
break;
431+
default:
432+
ret_val = -1;
434433
}
435434

436435
platform_exit_critical();
@@ -495,23 +494,26 @@ static uint8_t rf_convert_energy_level(uint8_t energyLevel)
495494
/**
496495
* SET MAC 16 address to Register
497496
*/
498-
static void rf_mac_set_shortAddress(uint8_t* valueAddress) {
497+
static void rf_mac_set_shortAddress(uint8_t *valueAddress)
498+
{
499499
ZLL->MACSHORTADDRS0 &= ~ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK;
500500
ZLL->MACSHORTADDRS0 |= ZLL_MACSHORTADDRS0_MACSHORTADDRS0(common_read_16_bit(valueAddress));
501501
}
502502

503503
/**
504504
* SET PAN-ID to Register
505505
*/
506-
static void rf_mac_set_panId(uint8_t* valueAddress) {
506+
static void rf_mac_set_panId(uint8_t *valueAddress)
507+
{
507508
ZLL->MACSHORTADDRS0 &= ~ZLL_MACSHORTADDRS0_MACPANID0_MASK;
508509
ZLL->MACSHORTADDRS0 |= ZLL_MACSHORTADDRS0_MACPANID0(common_read_16_bit(valueAddress));
509510
}
510511

511512
/**
512513
* SET MAC64 address to register
513514
*/
514-
static void rf_mac_set_mac64(const uint8_t* valueAddress) {
515+
static void rf_mac_set_mac64(const uint8_t *valueAddress)
516+
{
515517
ZLL->MACLONGADDRS0_MSB = common_read_32_bit(valueAddress);
516518
valueAddress += 4;
517519
ZLL->MACLONGADDRS0_LSB = common_read_32_bit(valueAddress);
@@ -544,7 +546,7 @@ static uint8_t PhyPlmeGetPwrLevelRequest(void)
544546

545547
static uint8_t PhyPlmeSetCurrentChannelRequest(uint8_t channel, uint8_t pan)
546548
{
547-
if((channel < 11) || (channel > 26)) {
549+
if ((channel < 11) || (channel > 26)) {
548550
return 1;
549551
}
550552

@@ -591,9 +593,9 @@ static void PhyIsrSeqCleanup(void)
591593
irqStatus |= ZLL_IRQSTS_TMR3MSK_MASK;
592594
/* Clear transceiver interrupts except TMRxIRQ */
593595
irqStatus &= ~(ZLL_IRQSTS_TMR1IRQ_MASK |
594-
ZLL_IRQSTS_TMR2IRQ_MASK |
595-
ZLL_IRQSTS_TMR3IRQ_MASK |
596-
ZLL_IRQSTS_TMR4IRQ_MASK);
596+
ZLL_IRQSTS_TMR2IRQ_MASK |
597+
ZLL_IRQSTS_TMR3IRQ_MASK |
598+
ZLL_IRQSTS_TMR4IRQ_MASK);
597599
ZLL->IRQSTS = irqStatus;
598600
}
599601

@@ -617,8 +619,8 @@ static void PhyIsrTimeoutCleanup(void)
617619
/* Mask TMR3 interrupt */
618620
irqStatus |= ZLL_IRQSTS_TMR3MSK_MASK;
619621
/* Clear transceiver interrupts except TMR1IRQ and TMR4IRQ. */
620-
irqStatus &= ~( ZLL_IRQSTS_TMR1IRQ_MASK |
621-
ZLL_IRQSTS_TMR4IRQ_MASK );
622+
irqStatus &= ~(ZLL_IRQSTS_TMR1IRQ_MASK |
623+
ZLL_IRQSTS_TMR4IRQ_MASK);
622624
ZLL->IRQSTS = irqStatus;
623625

624626
/* The packet was transmitted successfully, but no ACK was received */
@@ -686,19 +688,19 @@ static void rf_mac_hw_init(void)
686688
/* Enable 16 bit mode for TC2 - TC2 prime EN, disable all timers,
687689
enable AUTOACK, mask all interrupts */
688690
ZLL->PHY_CTRL = (gCcaCCA_MODE1_c << ZLL_PHY_CTRL_CCATYPE_SHIFT) |
689-
ZLL_PHY_CTRL_TC2PRIME_EN_MASK |
690-
ZLL_PHY_CTRL_TSM_MSK_MASK |
691-
ZLL_PHY_CTRL_WAKE_MSK_MASK |
692-
ZLL_PHY_CTRL_CRC_MSK_MASK |
693-
ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK |
694-
ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK |
695-
ZLL_PHY_CTRL_RX_WMRK_MSK_MASK |
696-
ZLL_PHY_CTRL_CCAMSK_MASK |
697-
ZLL_PHY_CTRL_RXMSK_MASK |
698-
ZLL_PHY_CTRL_TXMSK_MASK |
699-
ZLL_PHY_CTRL_SEQMSK_MASK |
700-
ZLL_PHY_CTRL_AUTOACK_MASK |
701-
ZLL_PHY_CTRL_TRCV_MSK_MASK;
691+
ZLL_PHY_CTRL_TC2PRIME_EN_MASK |
692+
ZLL_PHY_CTRL_TSM_MSK_MASK |
693+
ZLL_PHY_CTRL_WAKE_MSK_MASK |
694+
ZLL_PHY_CTRL_CRC_MSK_MASK |
695+
ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK |
696+
ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK |
697+
ZLL_PHY_CTRL_RX_WMRK_MSK_MASK |
698+
ZLL_PHY_CTRL_CCAMSK_MASK |
699+
ZLL_PHY_CTRL_RXMSK_MASK |
700+
ZLL_PHY_CTRL_TXMSK_MASK |
701+
ZLL_PHY_CTRL_SEQMSK_MASK |
702+
ZLL_PHY_CTRL_AUTOACK_MASK |
703+
ZLL_PHY_CTRL_TRCV_MSK_MASK;
702704

703705
/* Clear all PP IRQ bits to avoid unexpected interrupts immediately after init
704706
disable all timer interrupts */
@@ -927,7 +929,7 @@ static uint8_t rf_convert_LQI(uint8_t hwLqi)
927929
static void rf_handle_rx_end(void)
928930
{
929931
uint8_t rf_lqi = (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK) >>
930-
ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT;
932+
ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT;
931933
int8_t rf_rssi = 0;
932934
uint8_t len;
933935
uint8_t i;
@@ -944,7 +946,7 @@ static void rf_handle_rx_end(void)
944946
rf_rssi = rf_convert_LQI_to_RSSI(rf_lqi);
945947

946948
/* Load data from Packet Buffer */
947-
pPB = (uint8_t*)ZLL->PKT_BUFFER_RX;
949+
pPB = (uint8_t *)ZLL->PKT_BUFFER_RX;
948950

949951
for (i = 0; i < len; i++) {
950952
PHYPAYLOAD[i] = *pPB++;
@@ -978,8 +980,8 @@ static void handle_IRQ_events(void)
978980

979981
} else {
980982
/* Rx Watermark IRQ */
981-
if((!(ZLL->PHY_CTRL & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK)) &&
982-
(irqStatus & ZLL_IRQSTS_RXWTRMRKIRQ_MASK)) {
983+
if ((!(ZLL->PHY_CTRL & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK)) &&
984+
(irqStatus & ZLL_IRQSTS_RXWTRMRKIRQ_MASK)) {
983985
uint32_t rx_len = (irqStatus & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT;
984986

985987
/* Convert to symbols and add IFS and ACK duration */
@@ -1002,47 +1004,46 @@ static void handle_IRQ_events(void)
10021004
}
10031005
/* TMR3 timeout, the autosequence has been aborted due to TMR3 timeout */
10041006
else if ((irqStatus & ZLL_IRQSTS_TMR3IRQ_MASK) &&
1005-
(!(irqStatus & ZLL_IRQSTS_RXIRQ_MASK)) &&
1006-
(xcvseqCopy != gTX_c)) {
1007+
(!(irqStatus & ZLL_IRQSTS_RXIRQ_MASK)) &&
1008+
(xcvseqCopy != gTX_c)) {
10071009
PhyIsrTimeoutCleanup();
10081010
/* Start receiver */
10091011
rf_receive();
10101012
} else {
10111013
PhyIsrSeqCleanup();
1012-
switch(xcvseqCopy)
1013-
{
1014-
case gTX_c:
1015-
if ((ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCABFRTX_MASK) &&
1016-
(irqStatus & ZLL_IRQSTS_CCA_MASK)) {
1017-
device_driver.phy_tx_done_cb(rf_radio_driver_id, rf_mac_handle,
1018-
PHY_LINK_CCA_FAIL, 1, 1);
1019-
} else {
1020-
rf_handle_tx_end(false);
1021-
}
1022-
break;
1023-
1024-
case gTR_c:
1025-
if ((ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCABFRTX_MASK) &&
1026-
(irqStatus & ZLL_IRQSTS_CCA_MASK)) {
1027-
device_driver.phy_tx_done_cb(rf_radio_driver_id, rf_mac_handle,
1028-
PHY_LINK_CCA_FAIL, 1, 1);
1029-
} else {
1030-
rf_handle_tx_end((irqStatus & ZLL_IRQSTS_RX_FRM_PEND_MASK) > 0);
1031-
}
1032-
break;
1033-
1034-
case gRX_c:
1035-
rf_handle_rx_end();
1036-
break;
1037-
1038-
case gCCA_c:
1039-
rf_ed_value = rf_convert_energy_level((ZLL->LQI_AND_RSSI &
1040-
ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >>
1041-
ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT);
1042-
break;
1043-
1044-
default:
1045-
break;
1014+
switch (xcvseqCopy) {
1015+
case gTX_c:
1016+
if ((ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCABFRTX_MASK) &&
1017+
(irqStatus & ZLL_IRQSTS_CCA_MASK)) {
1018+
device_driver.phy_tx_done_cb(rf_radio_driver_id, rf_mac_handle,
1019+
PHY_LINK_CCA_FAIL, 1, 1);
1020+
} else {
1021+
rf_handle_tx_end(false);
1022+
}
1023+
break;
1024+
1025+
case gTR_c:
1026+
if ((ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCABFRTX_MASK) &&
1027+
(irqStatus & ZLL_IRQSTS_CCA_MASK)) {
1028+
device_driver.phy_tx_done_cb(rf_radio_driver_id, rf_mac_handle,
1029+
PHY_LINK_CCA_FAIL, 1, 1);
1030+
} else {
1031+
rf_handle_tx_end((irqStatus & ZLL_IRQSTS_RX_FRM_PEND_MASK) > 0);
1032+
}
1033+
break;
1034+
1035+
case gRX_c:
1036+
rf_handle_rx_end();
1037+
break;
1038+
1039+
case gCCA_c:
1040+
rf_ed_value = rf_convert_energy_level((ZLL->LQI_AND_RSSI &
1041+
ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >>
1042+
ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT);
1043+
break;
1044+
1045+
default:
1046+
break;
10461047
}
10471048
}
10481049
}
@@ -1097,7 +1098,7 @@ void NanostackRfPhyKw41z::get_mac_address(uint8_t *mac)
10971098
{
10981099
platform_enter_critical();
10991100

1100-
memcpy((void*)mac, (void*)MAC64_addr, sizeof(MAC64_addr));
1101+
memcpy((void *)mac, (void *)MAC64_addr, sizeof(MAC64_addr));
11011102

11021103
platform_exit_critical();
11031104
}
@@ -1111,7 +1112,7 @@ void NanostackRfPhyKw41z::set_mac_address(uint8_t *mac)
11111112
platform_exit_critical();
11121113
return;
11131114
}
1114-
memcpy((void*)MAC64_addr, (void*)mac, sizeof(MAC64_addr));
1115+
memcpy((void *)MAC64_addr, (void *)mac, sizeof(MAC64_addr));
11151116

11161117
platform_exit_critical();
11171118
}

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