Merge pull request #4445 from theotherjimmy/fix-exporters

Fixes for exporter issues

Author: 0xc0170

rtos/rtx5/TARGET_CORTEX_M/TARGET_M0/TOOLCHAIN_ARM/irq_cm0.s renamed to rtos/rtx5/TARGET_CORTEX_M/TARGET_M0/TOOLCHAIN_ARM/irq_cm0.S

@@ -202,14 +202,13 @@ def generate(self):
             print 'Build configuration: {0}'.format(opts['name'])
 
             profile = profiles[id]
-            profile_toolchain = profile[self.TOOLCHAIN]
 
             # A small hack, do not bother with src_path again,
             # pass an empty string to avoid crashing.
             src_paths = ['']
             target_name = self.toolchain.target.name
             toolchain = prepare_toolchain(
-                src_paths, "", target_name, self.TOOLCHAIN, build_profile=profile_toolchain)
+                src_paths, "", target_name, self.TOOLCHAIN, build_profile=[profile])
 
             # Hack to fill in build_dir
             toolchain.build_dir = self.toolchain.build_dir

rtos/rtx5/TARGET_CORTEX_M/TARGET_M0/TOOLCHAIN_IAR/irq_cm0.s renamed to rtos/rtx5/TARGET_CORTEX_M/TARGET_M0/TOOLCHAIN_IAR/irq_cm0.S

@@ -188,8 +188,5 @@
         "CExtraOptionsCheck": 1,
         "CExtraOptions": "--drv_vector_table_base=0x0",
         "CMSISDAPJtagSpeedList": 10
-    },
-    "REALTEK_RTL8195AM": {
-        "OGChipSelectEditMenu": "REALTEK_RTL8195AM\tRealtek REALTEK_RTL8195AM"
     }
 }

rtos/rtx5/TARGET_CORTEX_M/TARGET_M0P/TOOLCHAIN_ARM/irq_cm0.s renamed to rtos/rtx5/TARGET_CORTEX_M/TARGET_M0P/TOOLCHAIN_ARM/irq_cm0.S

@@ -39,8 +39,7 @@ class Makefile(Exporter):
         "MCU_NRF51Code.binary_hook",
         "TEENSY3_1Code.binary_hook",
         "LPCTargetCode.lpc_patch",
-        "LPC4088Code.binary_hook",
-        "RTL8195ACode.binary_hook"
+        "LPC4088Code.binary_hook"
     ])
 
     def generate(self):

rtos/rtx5/TARGET_CORTEX_M/TARGET_M0P/TOOLCHAIN_IAR/irq_cm0.s renamed to rtos/rtx5/TARGET_CORTEX_M/TARGET_M0P/TOOLCHAIN_IAR/irq_cm0.S

@@ -209,8 +209,12 @@ def generate(self):
         }
         core = ctx['device'].core
         ctx['cputype'] = core.rstrip("FD")
-        # Turn on FPU optimizations if the core has an FPU
-        ctx['fpu_setting'] = 1 if 'F' not in core or 'D' in core else 2
+        if core.endswith("FD"):
+            ctx['fpu_setting'] = 3
+        elif core.endswith("F"):
+            ctx['fpu_setting'] = 2
+        else:
+            ctx['fpu_setting'] = 1
         ctx['fputype'] = self.format_fpu(core)
         ctx.update(self.format_flags())
         self.gen_file('uvision/uvision.tmpl', ctx, self.project_name+".uvprojx")