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jeromecoutantLMESTM
jeromecoutant
authored and
LMESTM
committed
STM32L4: Add OSPI IP support in fallback QSPI mode
For STM32 platforms that embed an OSPI IP, we're offering a QSPI fallback support with this commit. When OSPI is supported in mbed, we can consider adding full OSPI support
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19 files changed

+602
-143
lines changed

19 files changed

+602
-143
lines changed

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h

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@@ -44,16 +44,6 @@ struct trng_s {
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RNG_HandleTypeDef handle;
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};
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47-
struct qspi_s {
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QSPI_HandleTypeDef handle;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#include "common_objects.h"
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#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h

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@@ -58,16 +58,6 @@ struct trng_s {
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RNG_HandleTypeDef handle;
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};
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struct qspi_s {
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QSPI_HandleTypeDef handle;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#include "common_objects.h"
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#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32F4/common_objects.h

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@@ -143,6 +143,23 @@ struct can_s {
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};
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#endif
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#if DEVICE_QSPI
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struct qspi_s {
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#if defined(OCTOSPI1)
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OSPI_HandleTypeDef handle;
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#else
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QSPI_HandleTypeDef handle;
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#endif
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QSPIName qspi;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#endif
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#ifdef __cplusplus
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}
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#endif

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h

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@@ -58,16 +58,6 @@ struct trng_s {
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RNG_HandleTypeDef handle;
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};
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struct qspi_s {
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QSPI_HandleTypeDef handle;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#include "common_objects.h"
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#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h

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@@ -58,16 +58,6 @@ struct trng_s {
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RNG_HandleTypeDef handle;
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};
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struct qspi_s {
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QSPI_HandleTypeDef handle;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#include "common_objects.h"
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#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h

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@@ -58,16 +58,6 @@ struct trng_s {
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RNG_HandleTypeDef handle;
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};
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struct qspi_s {
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QSPI_HandleTypeDef handle;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#include "common_objects.h"
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#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32F7/common_objects.h

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@@ -142,6 +142,23 @@ struct can_s {
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};
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#endif
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#if DEVICE_QSPI
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struct qspi_s {
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#if defined(OCTOSPI1)
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OSPI_HandleTypeDef handle;
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#else
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QSPI_HandleTypeDef handle;
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#endif
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QSPIName qspi;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#endif
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#ifdef __cplusplus
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}
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#endif

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h

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@@ -58,16 +58,6 @@ struct trng_s {
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RNG_HandleTypeDef handle;
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};
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struct qspi_s {
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QSPI_HandleTypeDef handle;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#include "common_objects.h"
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#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h

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@@ -58,16 +58,6 @@ struct trng_s {
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RNG_HandleTypeDef handle;
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};
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struct qspi_s {
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QSPI_HandleTypeDef handle;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#include "common_objects.h"
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#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h

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@@ -58,16 +58,6 @@ struct trng_s {
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RNG_HandleTypeDef handle;
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};
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struct qspi_s {
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QSPI_HandleTypeDef handle;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#include "common_objects.h"
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#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h

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@@ -58,16 +58,6 @@ struct trng_s {
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RNG_HandleTypeDef handle;
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};
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struct qspi_s {
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QSPI_HandleTypeDef handle;
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PinName io0;
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PinName io1;
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PinName io2;
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PinName io3;
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PinName sclk;
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PinName ssel;
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};
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#include "common_objects.h"
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#ifdef __cplusplus

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralNames.h

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@@ -83,6 +83,11 @@ typedef enum {
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CAN_1 = (int)CAN1_BASE
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} CANName;
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typedef enum {
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QSPI_1 = (int)OCTOSPI1_R_BASE,
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QSPI_2 = (int)OCTOSPI2_R_BASE
89+
} QSPIName;
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#ifdef __cplusplus
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}
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#endif

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralPins.c

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@@ -390,3 +390,59 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
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{PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to ARD_D9
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{NC, NC, 0}
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};
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//*** QUADSPI ***
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MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
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{PB_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0
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{PE_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO0 // Connected to D9
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{PF_0, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO0 // Connected to PSRAM_A0
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{PI_11, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO0 // Connected to OCTOSPIM_P2_IO0
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
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{PB_0, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 // Connected to ARD_A3
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{PE_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO1 // Connected to D10
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{PF_1, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO1 // Connected to PSRAM_A1
408+
{PI_10, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO1 // Connected to OCTOSPIM_P2_IO1
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{NC, NC, 0}
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};
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MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
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{PA_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 // Connected to ARD_A0
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{PE_14, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO2 // Connected to D11
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{PF_2, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO2 // Connected to PSRAM_A2
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{PI_9, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO2 // Connected to OCTOSPIM_P2_IO2
417+
{NC, NC, 0}
418+
};
419+
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MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
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{PA_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 // Connected to SPI2_CS
422+
{PE_15, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_IO3 // Connected to D12
423+
{PF_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO3 // Connected to PSRAM_A3
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{PH_8, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_IO3 // Connected to OCTOSPI_P2_IO3
425+
{NC, NC, 0}
426+
};
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MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
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// {PA_3, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK // Connected to STDIO_UART_RX
430+
{PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK // Connected to USART3_TX
431+
{PE_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK // Connected to D7
432+
{PF_4, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_CLK // Connected to PSRAM_A4
433+
{PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPIM_P1)}, // OCTOSPIM_P1_CLK
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{PI_6, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_CLK // Connected to OCTOSPIM_P2_CLK
435+
{NC, NC, 0}
436+
};
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MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
439+
// {PA_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS // Connected to STDIO_UART_TX
440+
{PA_4, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS // Connected to DCMI_HSYNC
441+
{PB_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS // Connected to USART3_RX
442+
{PC_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS // Connected to uSD_D3
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{PD_3, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P2)}, // OCTOSPIM_P2_NCS // Connected to PSRAM_CLK
444+
{PE_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)}, // OCTOSPIM_P1_NCS // Connected to D8
445+
{PG_12, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_NCS // Connected to OCTOSPIM_P2_CS
446+
{PI_5, QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)}, // OCTOSPIM_P2_NCS // Connected to DCMI_VSYNC
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{NC, NC, 0}
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};

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PinNames.h

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@@ -352,6 +352,14 @@ typedef enum {
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SYS_WKUP3 = PE_6,
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SYS_WKUP4 = PA_2,
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/**** QSPI FLASH pins ****/
356+
QSPI_FLASH1_IO0 = PI_11,
357+
QSPI_FLASH1_IO1 = PI_10,
358+
QSPI_FLASH1_IO2 = PI_9,
359+
QSPI_FLASH1_IO3 = PH_8,
360+
QSPI_FLASH1_SCK = PI_6,
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QSPI_FLASH1_CSN = PG_12,
362+
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/**** STMOD+ pins ****/
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STMOD_1 = PA_6,
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STMOD_2 = PB_15,

‎targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/objects.h

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