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dave-wudave-wu
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- Removed .mbedignore due to an issue with the eclipse exporter not picking up the ignored files;
- Added #includes in BSP data C files so they can be built on their own without mbedignore;
1 parent 9e0e9c8 commit d5122c5

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8 files changed

+41
-64
lines changed

8 files changed

+41
-64
lines changed

‎targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/.mbedignore

Lines changed: 0 additions & 28 deletions
This file was deleted.

‎targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/adc/adi_adc_data.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33

44
#include <drivers/adc/adi_adc.h>
55
#include <drivers/dma/adi_dma.h>
6+
#include <adi_processor.h>
67
#include "adi_adc_def.h"
78

89
/*! \cond PRIVATE */

‎targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/flash/adi_flash_data.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,10 +50,10 @@ POSSIBILITY OF SUCH DAMAGE.
5050

5151
/*! \cond PRIVATE */
5252

53+
#include <adi_processor.h>
5354
#include "adi_flash_def.h"
5455
#include "adi_flash_config.h"
5556

56-
5757
/* Stores the information about the specific device */
5858
static ADI_FEE_DEVICE_INFO fee_device_info [ADI_FEE_NUM_INSTANCES] =
5959
{

‎targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/i2c/adi_i2c_data.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,10 +49,10 @@ POSSIBILITY OF SUCH DAMAGE.
4949

5050
/*! \cond PRIVATE */
5151

52+
#include <adi_processor.h>
5253
#include "adi_i2c_def.h"
5354
#include "adi_i2c_config.h"
5455

55-
5656
/* Stores the information about the specific device */
5757
static ADI_I2C_DEVICE_INFO i2c_device_info [ADI_I2C_NUM_INSTANCES] =
5858
{

‎targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_data.c

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,10 @@ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5050
#define ADI_RTC_DATA_C_
5151

5252
#include <stdlib.h>
53+
#include <adi_processor.h>
5354
#include "adi_rtc_def.h"
5455

56+
5557
static ADI_RTC_DEVICE_INFO aRTCDeviceInfo[ADI_RTC_NUM_INSTANCE] =
5658
{
5759
{
@@ -100,7 +102,7 @@ static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] =
100102
0, /* CR7SSS */
101103
0, /* GPMUX0 */
102104
0 /* GPMUX1 */
103-
105+
104106
},
105107
/* RTC-1 */
106108
{
@@ -137,7 +139,7 @@ static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] =
137139
RTC1_CFG_TRIM_INTERVAL << BITP_RTC_TRM_IVL |
138140
RTC1_CFG_TRIM_OPERATION << BITP_RTC_TRM_ADD |
139141
RTC1_CFG_TRIM_VALUE << BITP_RTC_TRM_VALUE,
140-
142+
141143
/* CR2IC */
142144
RTC1_CFG_IC0_ENABLE << BITP_RTC_CR2IC_IC0EN |
143145
RTC1_CFG_IC2_ENABLE << BITP_RTC_CR2IC_IC2EN |
@@ -152,7 +154,7 @@ static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] =
152154
RTC1_CFG_IC3_EDGE_POLARITY << BITP_RTC_CR2IC_IC3LH |
153155
RTC1_CFG_IC4_EDGE_POLARITY << BITP_RTC_CR2IC_IC4LH |
154156
RTC1_CFG_IC_OVER_WRITE_ENABLE << BITP_RTC_CR2IC_ICOWUSEN,
155-
157+
156158
/* CR3SS */
157159
RTC1_CFG_SS1_ENABLE << BITP_RTC_CR3SS_SS1EN |
158160
RTC1_CFG_SS2_ENABLE << BITP_RTC_CR3SS_SS2EN |
@@ -172,16 +174,16 @@ static ADI_RTC_CONFIG aRTCConfig[ADI_RTC_NUM_INSTANCE] =
172174

173175
/* SSMSK */
174176
RTC1_CFG_SS1_MASK_VALUE,
175-
177+
176178
/* SS1 */
177179
RTC1_CFG_SS1_AUTO_RELOAD_VALUE,
178-
180+
179181
0, /* CR5SSS */ /* TODO: Add the following to the static configuration macros */
180182
0, /* CR6SSS */
181183
0, /* CR7SSS */
182184
0x4688, /* GPMUX0 */
183185
0x01F5, /* GPMUX1 */
184-
186+
185187
}
186188

187189
};

‎targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/rtc/adi_rtc_def.h

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/*!
22
*****************************************************************************
33
* @file: adi_rtc_def.h
4-
* @brief: RTC def file
4+
* @brief: RTC def file
55
* @version: $Revision: 33205 $
66
* @date: $Date: 2016-01-11 05:46:07 -0500 (Mon, 11 Jan 2016) $
77
*-----------------------------------------------------------------------------
@@ -46,10 +46,12 @@
4646
*****************************************************************************/
4747

4848
#ifndef ADI_RTC_DEF_H__
49-
#define ADI_RTC_DEF_H__
49+
#define ADI_RTC_DEF_H__
50+
51+
#include <drivers/rtc/adi_rtc.h>
5052

5153
/*! \cond PRIVATE */
52-
#define ADI_RTC_NUM_INSTANCE 2u
54+
#define ADI_RTC_NUM_INSTANCE 2u
5355

5456

5557

@@ -100,23 +102,23 @@
100102
#else
101103
/* pause on pending writes to CR to avoid data loss */
102104
#define PEND_BEFORE_WRITE(reg,mask)
103-
#define SYNC_AFTER_WRITE(reg,mask)
105+
#define SYNC_AFTER_WRITE(reg,mask)
104106
#endif
105107

106-
/*
108+
/*
107109
* The following is used for static configuration
108110
*/
109111
typedef struct
110112
{
111-
uint16_t CR0; /*!< CR0 16 bit control register-0 value */
113+
uint16_t CR0; /*!< CR0 16 bit control register-0 value */
112114
uint16_t CR1; /*!< CR1 16 bit control register-1 value */
113115
uint16_t CNT0; /*!< CNT0 16 bit count register value */
114116
uint16_t CNT1; /*!< CNT1 16 bit count register value */
115-
117+
116118
uint16_t ALM0; /*!< ALM0 16 bit integer part of alarm value */
117119
uint16_t ALM1; /*!< ALM1 16 bit integer part of alarm value */
118120
uint16_t ALM2; /*!< ALM2 16 bit integer part of alarm value */
119-
uint16_t TRIM; /*!< 16 bit trim register value */
121+
uint16_t TRIM; /*!< 16 bit trim register value */
120122
uint16_t CR2IC; /*!< CR2IC 16 bit control (which controls the input capture ) register-2 value */
121123
uint16_t CR3SS; /*!< CR3SS 16 bit control ( Controls enabling sensor strobe /IRQ etc )register-3 value */
122124
uint16_t CR4SS; /*!< CR4SS 16 bit control ( controls Auto reload and mask for sensor strobe ) register-4 value */
@@ -134,7 +136,7 @@ typedef struct
134136
typedef struct _ADI_RTC_DEVICE_INFO
135137
{
136138
volatile ADI_RTC_TypeDef *pRTCRegs; /* Base address of the SPORT registers */
137-
const IRQn_Type eIRQn; /* IRQn */
139+
const IRQn_Type eIRQn; /* IRQn */
138140
ADI_RTC_HANDLE hDevice; /* RTC handle */
139141
}ADI_RTC_DEVICE_INFO;
140142

@@ -146,10 +148,10 @@ typedef struct _ADI_RTC_DEVICE
146148
ADI_CALLBACK pfCallback; /* Function pointer for callback function. */
147149

148150
void *pCBParam; /* Parameter to callback function. */
149-
IRQn_Type eIRQn; /* IRQn */
151+
IRQn_Type eIRQn; /* IRQn */
150152
uint32_t cbWatch;
151153
ADI_RTC_DEVICE_INFO *pDeviceInfo; /* Parameter to callback function. */
152-
154+
153155
} ADI_RTC_DEVICE;
154156

155157

@@ -158,6 +160,6 @@ static void rtc_init(ADI_RTC_DEVICE *pDevice,ADI_RTC_CONFIG *pConfig);
158160
#ifdef ADI_DEBUG
159161
static ADI_RTC_RESULT ValidateHandle( ADI_RTC_DEVICE *pInDevice);
160162
#endif
161-
/*! \endcond */
163+
/*! \endcond */
162164
#endif /* ADI_RTC_DEF_H__ */
163165

‎targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/spi/adi_spi_data.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
/*
22
*****************************************************************************
33
* @file: adi_spi_data.c
4-
* @brief: Data declaration for SPORT Device Driver
4+
* @brief: Data declaration for SPORT Device Driver
55
*****************************************************************************
66
77
Copyright (c) 2016 Analog Devices, Inc.
@@ -49,6 +49,7 @@ POSSIBILITY OF SUCH DAMAGE.
4949

5050
/*! \cond PRIVATE */
5151

52+
#include <adi_processor.h>
5253
#include "adi_spi_def.h"
5354
#include "adi_spi_config.h"
5455
#include <drivers/dma/adi_dma.h>
@@ -109,7 +110,7 @@ static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] =
109110

110111
/**** SPI_DIV buad rate selection register *** */
111112
(((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI0_CFG_BIT_RATE)) >>1u)-1u))\
112-
<< BITP_SPI_DIV_VALUE )
113+
<< BITP_SPI_DIV_VALUE )
113114
},
114115
/* Initialize SPI1 Instance configuration. */
115116
{
@@ -131,7 +132,7 @@ static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] =
131132

132133
/**** SPI_DIV buad rate selection register *** */
133134
(((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI1_CFG_BIT_RATE)) >>1u)-1u))\
134-
<< BITP_SPI_DIV_VALUE )
135+
<< BITP_SPI_DIV_VALUE )
135136
},
136137
/* Initialize SPI2 Instance configuration. */
137138
{
@@ -153,7 +154,7 @@ static const ADI_SPI_CFG_TYPE gSPICfg[ADI_SPI_NUM_INSTANCES] =
153154

154155
/**** SPI_DIV buad rate selection register *** */
155156
(((((ADI_CFG_SYSTEM_CLOCK_HZ / (ADI_SPI2_CFG_BIT_RATE)) >>1u)-1u))\
156-
<< BITP_SPI_DIV_VALUE )
157+
<< BITP_SPI_DIV_VALUE )
157158
}
158159
};
159160

‎targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -46,18 +46,17 @@ POSSIBILITY OF SUCH DAMAGE.
4646
#ifndef ADI_TMR_DATA
4747
#define ADI_TMR_DATA
4848

49-
49+
#include <adi_processor.h>
5050
#include <stdlib.h>
5151
#include <adi_tmr_config.h>
5252
#include <drivers/tmr/adi_tmr.h>
5353

54-
5554
/* CTL register static configuration */
56-
static uint16_t aTimerCtlConfig[] =
55+
static uint16_t aTimerCtlConfig[] =
5756
{
5857
(TMR0_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
5958
(TMR0_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
60-
(TMR0_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
59+
(TMR0_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
6160
(TMR0_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
6261
(TMR0_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
6362
(TMR0_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
@@ -66,7 +65,7 @@ static uint16_t aTimerCtlConfig[] =
6665

6766
(TMR1_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
6867
(TMR1_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
69-
(TMR1_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
68+
(TMR1_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
7069
(TMR1_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
7170
(TMR1_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
7271
(TMR1_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
@@ -75,7 +74,7 @@ static uint16_t aTimerCtlConfig[] =
7574

7675
(TMR2_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
7776
(TMR2_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
78-
(TMR2_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
77+
(TMR2_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
7978
(TMR2_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
8079
(TMR2_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
8180
(TMR2_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
@@ -84,16 +83,16 @@ static uint16_t aTimerCtlConfig[] =
8483

8584
(TMR3_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
8685
(TMR3_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
87-
(TMR3_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
86+
(TMR3_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
8887
(TMR3_CFG_CLOCK_SOURCE << BITP_TMR_RGB_CTL_CLK) |
8988
(TMR3_CFG_ENABLE_RELOADING << BITP_TMR_RGB_CTL_RLD) |
9089
(TMR3_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
9190
(TMR3_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) |
92-
(TMR3_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
91+
(TMR3_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
9392
};
9493

9594
/* LOAD register static configuration */
96-
static uint16_t aTimerLoadConfig[] =
95+
static uint16_t aTimerLoadConfig[] =
9796
{
9897
TMR0_CFG_LOAD_VALUE,
9998
TMR1_CFG_LOAD_VALUE,
@@ -102,7 +101,7 @@ static uint16_t aTimerLoadConfig[] =
102101
};
103102

104103
/* Asynchronous LOAD static configuraton */
105-
static uint16_t aTimerALoadConfig[] =
104+
static uint16_t aTimerALoadConfig[] =
106105
{
107106
TMR0_CFG_ASYNC_LOAD_VALUE,
108107
TMR1_CFG_ASYNC_LOAD_VALUE,
@@ -135,10 +134,10 @@ static uint16_t aTimerPwmCtlConfig[] =
135134
(TMR3_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
136135

137136
(TMR3_CFG_PWM1_IDLE_STATE << BITP_TMR_RGB_PWM1CTL_IDLESTATE) |
138-
(TMR3_CFG_PWM1_MATCH_VALUE << BITP_TMR_RGB_PWM1CTL_MATCH),
137+
(TMR3_CFG_PWM1_MATCH_VALUE << BITP_TMR_RGB_PWM1CTL_MATCH),
139138

140139
(TMR3_CFG_PWM2_IDLE_STATE << BITP_TMR_RGB_PWM2CTL_IDLESTATE) |
141-
(TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH),
140+
(TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH),
142141
};
143142

144143
/* PWM MATCH static configuration */

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