|
2951 | 2951 | },
|
2952 | 2952 | "EFR32MG12P332F1024GL125": {
|
2953 | 2953 | "inherits": ["EFM32"],
|
2954 |
| - "extra_labels_add": ["EFR32MG12", "EFR32_12", "1024K", "SL_RAIL", "SL_CRYPTO"], |
| 2954 | + "extra_labels_add": ["EFR32_12", "EFR32MG12", "EFR32_12", "1024K", "SL_RAIL", "SL_CRYPTO"], |
2955 | 2955 | "core": "Cortex-M4F",
|
2956 | 2956 | "macros_add": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
|
2957 | 2957 | "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
|
|
2999 | 2999 | },
|
3000 | 3000 | "EFR32FG1P132F256GM48": {
|
3001 | 3001 | "inherits": ["EFM32"],
|
3002 |
| - "extra_labels_add": ["EFR32FG1", "256K", "SL_RAIL", "SL_CRYPTO"], |
| 3002 | + "extra_labels_add": ["EFR32_1", "EFR32FG1", "256K", "SL_RAIL", "SL_CRYPTO"], |
3003 | 3003 | "core": "Cortex-M4F",
|
3004 |
| - "macros": ["EFR32FG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4", "INITIAL_SP=0x20005000UL"], |
| 3004 | + "macros": ["EFR32FG1", "EFR32FG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"], |
3005 | 3005 | "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
|
3006 | 3006 | "release_versions": ["2", "5"],
|
3007 | 3007 | "public": false,
|
|
3052 | 3052 | },
|
3053 | 3053 | "EFR32FG12P433F1024GL125": {
|
3054 | 3054 | "inherits": ["EFM32"],
|
3055 |
| - "extra_labels_add": ["EFR32FG12", "256K", "SL_RAIL", "SL_CRYPTO"], |
| 3055 | + "extra_labels_add": ["EFR32_12", "EFR32FG12", "256K", "SL_RAIL", "SL_CRYPTO"], |
3056 | 3056 | "core": "Cortex-M4F",
|
3057 |
| - "macros": ["EFR32FG12P433F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4", "INITIAL_SP=0x20005000UL"], |
| 3057 | + "macros": ["EFR32FG12", "EFR32FG12P433F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"], |
3058 | 3058 | "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
|
3059 | 3059 | "release_versions": ["2", "5"],
|
3060 | 3060 | "public": false,
|
|
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