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Merge pull request #10156 from juhoeskeli/MTB_STM_L475_uart_clock_fix
MTB_STM_L475: fix UART clock
2 parents f99431f + a3beb10 commit d850d3b

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  • targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475

1 file changed

+8
-12
lines changed

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c

Lines changed: 8 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -171,11 +171,12 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
171171
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
172172

173173
// Enable HSE oscillator and activate PLL with HSE as source
174-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
174+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI;
175175
if (bypass == 0) {
176-
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
176+
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
177+
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
177178
} else {
178-
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
179+
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
179180
}
180181
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
181182
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
@@ -200,15 +201,10 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
200201
return 0; // FAIL
201202
}
202203

203-
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
204-
RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
205-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
206-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
207-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
208-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
209-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
210-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
211-
RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
204+
// Select LSE output as LPUART1 clock source
205+
RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPUART1;
206+
RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
207+
RCC_PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
212208
if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
213209
return 0; // FAIL
214210
}

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