Merge pull request #6273 from bulislaw/update_cmsis_5.3

Update cmsis/rtx to version 5.3

Author: 0xc0170

cmsis/RTE_Components.h

@@ -18,16 +18,7 @@
 
 #define CMSIS_device_header <cmsis.h>
 
-#ifndef MBED_CONF_TZ_PROCESS_STACK_SIZE
-#define MBED_CONF_TZ_PROCESS_STACK_SIZE  512
-#endif
-#ifndef MBED_CONF_TZ_PROCESS_STACK_SLOTS
-#define MBED_CONF_TZ_PROCESS_STACK_SLOTS  8
-#endif
-
-#define TZ_PROCESS_STACK_SLOTS  MBED_CONF_TZ_PROCESS_STACK_SLOTS
-#define TZ_PROCESS_STACK_SIZE  MBED_CONF_TZ_PROCESS_STACK_SIZE
+#include "mbed_rtx_conf.h"
+#include "mbed_cmsis_conf.h"
 
 #endif
-
-

cmsis/TARGET_CORTEX_A/cmsis_armcc.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_armcc.h
  * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.0.1
- * @date     07. Sep 2017
+ * @version  V1.0.2
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -26,7 +26,7 @@
 #define __CMSIS_ARMCC_H
 
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
 #endif
 
 /* CMSIS compiler control architecture macros */

cmsis/TARGET_CORTEX_A/cmsis_armclang.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_armclang.h
  * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.0.1
- * @date     07. Sep 2017
+ * @version  V1.0.2
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,7 +28,7 @@
 #pragma clang system_header   /* treat file as system include file */
 
 #ifndef __ARM_COMPAT_H
-#include <arm_compat.h>    /* Compatibility header for ARM Compiler 5 intrinsics */
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
 #endif
 
 /* CMSIS compiler specific defines */

cmsis/TARGET_CORTEX_A/cmsis_compiler.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
  * @file     cmsis_compiler.h
  * @brief    CMSIS compiler specific macros, functions, instructions
- * @version  V1.0.1
- * @date     01. December 2017
+ * @version  V1.0.2
+ * @date     10. January 2018
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,14 +28,14 @@
 #include <stdint.h>
 
 /*
- * ARM Compiler 4/5
+ * Arm Compiler 4/5
  */
 #if   defined ( __CC_ARM )
   #include "cmsis_armcc.h"
 
 
 /*
- * ARM Compiler 6 (armclang)
+ * Arm Compiler 6 (armclang)
  */
 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
   #include "cmsis_armclang.h"
@@ -56,7 +56,7 @@
 
 
 /*
- * TI ARM Compiler
+ * TI Arm Compiler
  */
 #elif defined ( __TI_ARM__ )
   #include <cmsis_ccs.h>

cmsis/TARGET_CORTEX_A/cmsis_cp15.h

@@ -223,7 +223,7 @@ __STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
   return result;
 }
 
- /** \brief  Get VBAR
+/** \brief  Get VBAR
 
     This function returns the value of the Vector Base Address Register.
 
@@ -244,7 +244,31 @@ __STATIC_FORCEINLINE uint32_t __get_VBAR(void)
  */
 __STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
 {
-  __set_CP(15, 0, vbar, 12, 0, 1);
+  __set_CP(15, 0, vbar, 12, 0, 0);
+}
+
+/** \brief  Get MVBAR
+
+    This function returns the value of the Monitor Vector Base Address Register.
+
+    \return               Monitor Vector Base Address Register
+ */
+__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
+{
+  uint32_t result;
+  __get_CP(15, 0, result, 12, 0, 1);
+  return result;
+}
+
+/** \brief  Set MVBAR
+
+    This function assigns the given value to the Monitor Vector Base Address Register.
+
+    \param [in]    mvbar  Monitor Vector Base Address Register value to set
+ */
+__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
+{
+  __set_CP(15, 0, mvbar, 12, 0, 1);
 }
 
 #if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
@@ -413,13 +437,32 @@ __STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
   __set_CP(15, 0, value, 7, 14, 1);
 }
 
+/** \brief  Set CSSELR
+ */
+__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
+{
+//  __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
+  __set_CP(15, 2, value, 0, 0, 0);
+}
+
+/** \brief  Get CSSELR
+    \return CSSELR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
+{
+  uint32_t result;
+//  __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
+  __get_CP(15, 2, result, 0, 0, 0);
+  return result;
+}
 
 /** \brief  Set CCSIDR
+    \deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
  */
+CMSIS_DEPRECATED
 __STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
 {
-//  __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
-  __set_CP(15, 2, value, 0, 0, 0);
+  __set_CSSELR(value);
 }
 
 /** \brief  Get CCSIDR

cmsis/TARGET_CORTEX_A/cmsis_gcc.h

@@ -642,7 +642,7 @@ __STATIC_INLINE void __FPU_Enable(void)
     "        VMOV    D14,R2,R2         \n"
     "        VMOV    D15,R2,R2         \n"
 
-#if __ARM_NEON == 1
+#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
     //Initialise D32 registers to 0
     "        VMOV    D16,R2,R2         \n"
     "        VMOV    D17,R2,R2         \n"

cmsis/TARGET_CORTEX_A/cmsis_iccarm.h

@@ -1,13 +1,13 @@
 /**************************************************************************//**
  * @file     cmsis_iccarm.h
- * @brief    CMSIS compiler ICCARM (IAR compiler) header file
- * @version  V5.0.4
- * @date     01. December 2017
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.5
+ * @date     10. January 2018
  ******************************************************************************/
 
 //------------------------------------------------------------------------------
 //
-// Copyright (c) 2017 IAR Systems
+// Copyright (c) 2017-2018 IAR Systems
 //
 // Licensed under the Apache License, Version 2.0 (the "License")
 // you may not use this file except in compliance with the License.

cmsis/TARGET_CORTEX_A/core_ca.h

@@ -950,8 +950,8 @@ __STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
 */
 __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
 {
-  register volatile uint32_t Dummy;
-  register volatile uint32_t ccsidr;
+  uint32_t Dummy;
+  uint32_t ccsidr;
   uint32_t num_sets;
   uint32_t num_ways;
   uint32_t shift_way;
@@ -960,7 +960,7 @@ __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t ma
 
   Dummy = level << 1U;
   /* set csselr, select ccsidr register */
-  __set_CCSIDR(Dummy);
+  __set_CSSELR(Dummy);
   /* get current ccsidr register */
   ccsidr = __get_CCSIDR();
   num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
@@ -992,7 +992,7 @@ __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t ma
 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
 */
 __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
-  register volatile uint32_t clidr;
+  uint32_t clidr;
   uint32_t cache_type;
   clidr =  __get_CLIDR();
   for(uint32_t i = 0U; i<7U; i++)

cmsis/TARGET_CORTEX_A/irq_ctrl.h

@@ -22,6 +22,12 @@
  * limitations under the License.
  */
 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
 #ifndef IRQ_CTRL_H_
 #define IRQ_CTRL_H_
 

cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c

@@ -24,7 +24,8 @@
 
 #include <stddef.h>
 
-#include <cmsis.h>
+#include "RTE_Components.h"
+#include CMSIS_device_header
 
 #include "irq_ctrl.h"
 
@@ -125,13 +126,11 @@ __WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
 
 /// Configure interrupt request mode.
 __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
-  int32_t status;
   uint32_t val;
   uint8_t cfg;
   uint8_t secure;
   uint8_t cpu;
-
-  status = 0;
+  int32_t status = 0;
 
   if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
     // Check triggering mode
@@ -142,6 +141,7 @@ __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
     } else if (val == IRQ_MODE_TRIG_EDGE) {
       cfg = 0x02U;
     } else {
+      cfg = 0x00U;
       status = -1;
     }
 
@@ -156,15 +156,16 @@ __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
     val = mode & IRQ_MODE_DOMAIN_Msk;
 
     if (val == IRQ_MODE_DOMAIN_NONSECURE) {
-      secure = 0;
+      secure = 0U;
     } else {
       // Check security extensions support
       val = GIC_DistributorInfo() & (1UL << 10U);
 
       if (val != 0U) {
         // Security extensions are supported
-        secure = 1;
+        secure = 1U;
       } else {
+        secure = 0U;
         status = -1;
       }
     }
@@ -173,7 +174,7 @@ __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
     val = mode & IRQ_MODE_CPU_Msk;
 
     if (val == IRQ_MODE_CPU_ALL) {
-      cpu = 0xFF;
+      cpu = 0xFFU;
     } else {
       cpu = val >> IRQ_MODE_CPU_Pos;
     }