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Merge pull request #5824 from jeromecoutant/DEV_DISCO_F407
DISCO_F407VG : alignment with other STM32
2 parents 8c78649 + 0eede79 commit debca1f

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5 files changed

+715
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‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/PinNames.h

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -197,13 +197,13 @@ typedef enum {
197197
ADC_VBAT = 0xF2,
198198

199199
// Generic signals namings
200-
LED1 = PD_13,
201-
LED2 = PD_12,
202-
LED3 = PD_13,
203-
LED4 = PD_12,
204-
LED5 = PD_14,
205-
LED6 = PD_15,
206-
LED_RED = LED1,
200+
LED1 = PD_13, // LD3 as LD1 is not a user LED
201+
LED2 = PD_12, // LD4 as LD2 is not a user LED
202+
LED3 = PD_13, // orange
203+
LED4 = PD_12, // green
204+
LED5 = PD_14, // red
205+
LED6 = PD_15, // blue
206+
LED_RED = LED5,
207207
USER_BUTTON = PA_0,
208208
// Standardized button names
209209
BUTTON1 = USER_BUTTON,

‎targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c

Lines changed: 31 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -17,25 +17,20 @@
1717
/**
1818
* This file configures the system clock as follows:
1919
*-----------------------------------------------------------------------------
20-
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
21-
* | (external 8 MHz clock) | (internal 16 MHz)
22-
* | 2- PLL_HSE_XTAL |
23-
* | (external 8 MHz xtal) |
20+
* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
21+
* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
22+
* | 3- USE_PLL_HSI (internal 16 MHz)
2423
*-----------------------------------------------------------------------------
25-
* SYSCLK(MHz) | 168 | 168
26-
*-----------------------------------------------------------------------------
27-
* AHBCLK (MHz) | 168 | 168
28-
*-----------------------------------------------------------------------------
29-
* APB1CLK (MHz) | 42 | 42
30-
*-----------------------------------------------------------------------------
31-
* APB2CLK (MHz) | 84 | 84
32-
*-----------------------------------------------------------------------------
33-
* USB capable (48 MHz precise clock) | YES | NO
24+
* SYSCLK(MHz) | 168
25+
* AHBCLK (MHz) | 168
26+
* APB1CLK (MHz) | 42
27+
* APB2CLK (MHz) | 84
28+
* USB capable | YES
3429
*-----------------------------------------------------------------------------
3530
**/
3631

3732
#include "stm32f4xx.h"
38-
33+
#include "mbed_assert.h"
3934

4035
/*!< Uncomment the following line if you need to relocate your vector Table in
4136
Internal SRAM. */
@@ -44,16 +39,20 @@
4439
This value must be a multiple of 0x200. */
4540

4641

47-
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
48-
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
49-
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
42+
// clock source is selected with CLOCK_SOURCE in json config
43+
#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
44+
#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
45+
#define USE_PLL_HSI 0x2 // Use HSI internal clock
5046

5147

52-
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
48+
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
5349
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
54-
#endif
50+
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
5551

52+
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
5653
uint8_t SetSysClock_PLL_HSI(void);
54+
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
55+
5756

5857
/**
5958
* @brief Setup the microcontroller system
@@ -110,20 +109,23 @@ void SystemInit(void)
110109
*/
111110
void SetSysClock(void)
112111
{
112+
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
113113
/* 1- Try to start with HSE and external clock */
114-
#if USE_PLL_HSE_EXTC != 0
115114
if (SetSysClock_PLL_HSE(1) == 0)
116115
#endif
117116
{
117+
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
118118
/* 2- If fail try to start with HSE and external xtal */
119-
#if USE_PLL_HSE_XTAL != 0
120119
if (SetSysClock_PLL_HSE(0) == 0)
121120
#endif
122121
{
122+
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
123123
/* 3- If fail start with HSI clock */
124-
if (SetSysClock_PLL_HSI() == 0) {
124+
if (SetSysClock_PLL_HSI() == 0)
125+
#endif
126+
{
125127
while(1) {
126-
// [TODO] Put something here to tell the user that a problem occured...
128+
MBED_ASSERT(1);
127129
}
128130
}
129131
}
@@ -133,14 +135,14 @@ void SetSysClock(void)
133135
//HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_1); // 84 MHz
134136
}
135137

136-
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
138+
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
137139
/******************************************************************************/
138140
/* PLL (clocked by HSE) used as System clock source */
139141
/******************************************************************************/
140142
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
141143
{
142-
RCC_ClkInitTypeDef RCC_ClkInitStruct;
143144
RCC_OscInitTypeDef RCC_OscInitStruct;
145+
RCC_ClkInitTypeDef RCC_ClkInitStruct;
144146

145147
/* The voltage scaling allows optimizing the power consumption when the device is
146148
clocked below the maximum system frequency, to update the voltage scaling value
@@ -186,15 +188,16 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
186188

187189
return 1; // OK
188190
}
189-
#endif
191+
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
190192

193+
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
191194
/******************************************************************************/
192195
/* PLL (clocked by HSI) used as System clock source */
193196
/******************************************************************************/
194197
uint8_t SetSysClock_PLL_HSI(void)
195198
{
196-
RCC_ClkInitTypeDef RCC_ClkInitStruct;
197199
RCC_OscInitTypeDef RCC_OscInitStruct;
200+
RCC_ClkInitTypeDef RCC_ClkInitStruct;
198201

199202
/* The voltage scaling allows optimizing the power consumption when the device is
200203
clocked below the maximum system frequency, to update the voltage scaling value
@@ -232,3 +235,4 @@ uint8_t SetSysClock_PLL_HSI(void)
232235

233236
return 1; // OK
234237
}
238+
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

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