Merge pull request #13797 from JojoS62/PR_fix_LSE-drive-load-setting

STM32: add setting for LSE drive load level

Author: 0xc0170

targets/TARGET_STM/TARGET_STM32L5/system_clock.c

@@ -134,7 +134,6 @@ uint8_t SetSysClock_PLL_MSI(void)
     __HAL_RCC_RTCAPB_CLK_ENABLE();
 
 #if MBED_CONF_TARGET_LSE_AVAILABLE
-    __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
     RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
     RCC_OscInitStruct.LSEState       = RCC_LSE_ON;   // External 32.768 kHz clock on OSC_IN/OSC_OUT

targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c

@@ -72,7 +72,6 @@ void SetSysClock(void)
 
     Config_HSE();
 
-    __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
     /* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */

targets/TARGET_STM/mbed_overrides.c

@@ -27,10 +27,69 @@
  */
 #include "cmsis.h"
 #include "objects.h"
+#include "platform/mbed_error.h"
 
 int mbed_sdk_inited = 0;
 extern void SetSysClock(void);
 
+#if defined(RCC_LSE_HIGHDRIVE_MODE) || defined(RCC_LSEDRIVE_HIGH)
+#   define LSE_CONFIG_AVAILABLE
+#endif
+
+// set defaults for LSE drive load level
+#if defined(LSE_CONFIG_AVAILABLE)
+
+#   if defined(MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL)
+#       define LSE_DRIVE_LOAD_LEVEL    MBED_CONF_TARGET_LSE_DRIVE_LOAD_LEVEL
+#   else
+#       if defined(RCC_LSE_HIGHDRIVE_MODE)
+#           define LSE_DRIVE_LOAD_LEVEL    RCC_LSE_LOWPOWER_MODE
+#       else
+#           define LSE_DRIVE_LOAD_LEVEL    RCC_LSEDRIVE_LOW
+#       endif
+#   endif
+
+
+/**
+ * @brief configure the LSE crystal driver load
+ * This settings ist target hardware dependend and 
+ * depends on the crystal that is used for LSE clock.
+ * For low power requirements, crystals with low load capacitors can be used and
+ * driver setting is RCC_LSEDRIVE_LOW.
+ * For higher stablity, crystals with higher load capacitys can be used and
+ * driver setting is RCC_LSEDRIVE_HIGH.
+ * 
+ * A detailed description about this setting can be found here:
+ * https://www.st.com/resource/en/application_note/cd00221665-oscillator-design-guide-for-stm8afals-stm32-mcus-and-mpus-stmicroelectronics.pdf
+ * 
+ * LSE maybe used later, but crystal load drive setting is necessary before 
+ * enabling LSE.
+ *   
+ * @param None
+ * @retval None
+ */
+
+static void LSEDriveConfig(void) {
+    // this config can be changed only when LSE is stopped
+    // LSE could be enabled before a reset and will remain running, disable first
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+    {
+        error("LSEDriveConfig : failed to disable LSE\n");
+    }
+
+   // set LSE drive level. Exception only for F4_g2 series
+    HAL_PWR_EnableBkUpAccess();
+    #if defined(__HAL_RCC_LSEDRIVE_CONFIG)
+        __HAL_RCC_LSEDRIVE_CONFIG(LSE_DRIVE_LOAD_LEVEL);
+    #else
+        HAL_RCCEx_SelectLSEMode(LSE_DRIVE_LOAD_LEVEL);
+    #endif
+}
+#endif  // LSE_CONFIG_AVAILABLE
+
 /**
  * @brief Setup the target board-specific configuration
  * of the microcontroller
@@ -120,6 +179,11 @@ void mbed_sdk_init()
 
     /* Configure the System clock source, PLL Multiplier and Divider factors,
        AHB/APBx prescalers and Flash settings */
+#if defined(LSE_CONFIG_AVAILABLE)
+    // LSE maybe used later, but crystal load drive setting is necessary before 
+    // enabling LSE
+    LSEDriveConfig();
+#endif
     SetSysClock();
     SystemCoreClockUpdate();
 
@@ -142,6 +206,9 @@ void mbed_sdk_init()
 
     /* Configure the System clock source, PLL Multiplier and Divider factors,
        AHB/APBx prescalers and Flash settings */
+#if defined(LSE_CONFIG_AVAILABLE)
+    LSEDriveConfig();
+#endif
     SetSysClock();
     SystemCoreClockUpdate();
 #endif /* DUAL_CORE */

targets/targets.json

@@ -1198,6 +1198,11 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lse_drive_load_level": {
+                "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
+                "value": "RCC_LSEDRIVE_LOW",
+                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
             }
         },
         "macros_add": [
@@ -1407,6 +1412,11 @@
                 "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
                 "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
                 "macro_name": "CLOCK_SOURCE"
+            },
+            "lse_drive_load_level": {
+                "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
+                "value": "RCC_LSEDRIVE_LOW",
+                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
             }
         },
         "device_has_add": [
@@ -2165,6 +2175,11 @@
             "lpticker_lptim": {
                 "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
                 "value": 1
+            },
+            "lse_drive_load_level": {
+                "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
+                "value": "RCC_LSEDRIVE_LOW",
+                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
             }
         },
         "overrides": {
@@ -2408,6 +2423,11 @@
             "lpticker_lptim": {
                 "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
                 "value": 1
+            },
+            "lse_drive_load_level": {
+                "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
+                "value": "RCC_LSEDRIVE_LOW",
+                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
             }
         },
         "extra_labels_add": [
@@ -2511,6 +2531,11 @@
             "lpticker_lptim": {
                 "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
                 "value": 1
+            },
+            "lse_drive_load_level": {
+                "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
+                "value": "RCC_LSEDRIVE_LOW",
+                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
             }
         },
         "extra_labels_add": [
@@ -2674,6 +2699,11 @@
             "lpticker_lptim": {
                 "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
                 "value": 1
+            },
+            "lse_drive_load_level": {
+                "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
+                "value": "RCC_LSEDRIVE_LOW",
+                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
             }
         },
         "components_add": [
@@ -2937,6 +2967,11 @@
             "lpticker_lptim": {
                 "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
                 "value": 1
+            },
+            "lse_drive_load_level": {
+                "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
+                "value": "RCC_LSEDRIVE_LOW",
+                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
             }
         },
         "macros_add": [
@@ -3170,6 +3205,11 @@
             "lpticker_lptim": {
                 "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
                 "value": 1
+            },
+            "lse_drive_load_level": {
+                "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
+                "value": "RCC_LSEDRIVE_LOW",
+                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
             }
         },
         "macros_add": [
@@ -3701,6 +3741,11 @@
             "lpticker_lptim": {
                 "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
                 "value": 1
+            },
+            "lse_drive_load_level": {
+                "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
+                "value": "RCC_LSEDRIVE_LOW",
+                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
             }
         },
         "overrides": {
@@ -3800,6 +3845,11 @@
             "lpticker_lptim": {
                 "help": "This target supports LPTIM. Set value 1 to use LPTIM for LPTICKER, or 0 to use RTC wakeup timer",
                 "value": 1
+            },
+            "lse_drive_load_level": {
+                "help": "HSE drive load level  RCC_LSEDRIVE_LOW | RCC_LSEDRIVE_MEDIUMLOW | RCC_LSEDRIVE_MEDIUMHIGH | RCC_LSEDRIVE_HIGH",
+                "value": "RCC_LSEDRIVE_LOW",
+                "macro_name": "TARGET_LSE_DRIVE_LOAD_LEVEL"
             }
         },
         "macros_add": [