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TacoGrandeTXTacoGrandeTX
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Changes required for rebase:
 - Brought in new nrfx APIs - Brought in PPI additions - Removed dead code for RTC
1 parent 7468896 commit e2eb85a

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+26
-46
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1 file changed

+26
-46
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‎targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF52/serial_api.c

Lines changed: 26 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,8 @@
4646
#include "app_util_platform.h"
4747
#include "pinmap_ex.h"
4848
#include "nrfx_glue.h"
49+
#include "nrfx_gpiote.h"
50+
#include "nrfx_ppi.h"
4951

5052
#include "platform/mbed_critical.h"
5153

@@ -136,7 +138,7 @@ typedef struct {
136138
nrf_atfifo_t *fifo;
137139
uint32_t fifo_free_count;
138140
nrf_ppi_channel_t ppi_rts;
139-
nrf_drv_gpiote_pin_t rts;
141+
nrfx_gpiote_pin_t rts;
140142
bool rx_suspended;
141143
} nordic_uart_state_t;
142144

@@ -190,8 +192,8 @@ NRF_ATFIFO_DEF(nordic_nrf5_uart_fifo_1, uint8_t, UART1_FIFO_BUFFER_SIZE);
190192
*/
191193
static uint8_t nordic_nrf5_uart_swi_mask_tx_0 = 0;
192194
static uint8_t nordic_nrf5_uart_swi_mask_rx_0 = 0;
193-
static uint8_t nordic_nrf5_uart_swi_mask_tx_1 = 0;
194-
static uint8_t nordic_nrf5_uart_swi_mask_rx_1 = 0;
195+
//static uint8_t nordic_nrf5_uart_swi_mask_tx_1 = 0;
196+
//static uint8_t nordic_nrf5_uart_swi_mask_rx_1 = 0;
195197

196198
/**
197199
* Global variables expected by mbed_retarget.cpp for STDOUT.
@@ -453,7 +455,7 @@ static void nordic_nrf5_uart_event_handler_rxstarted(int instance)
453455
if (nordic_nrf5_uart_state[instance].rts != NRF_UART_PSEL_DISCONNECTED) {
454456
if (nordic_nrf5_uart_state[instance].fifo_free_count > FIFO_MIN) {
455457
/* Clear rts since we are ready to receive the next byte */
456-
nrf_drv_gpiote_clr_task_trigger(nordic_nrf5_uart_state[instance].rts);
458+
nrfx_gpiote_clr_task_trigger(nordic_nrf5_uart_state[instance].rts);
457459
} else {
458460
/* Suspend reception since there isn't enough buffer space.
459461
* The function serial_getc will restart reception. */
@@ -625,43 +627,43 @@ static void nordic_nrf5_uart_configure_object(serial_t *obj)
625627
uint32_t ret;
626628

627629
/* Disable the PPI interconnect */
628-
ret = nrf_drv_ppi_channel_disable(nordic_nrf5_uart_state[uart_object->instance].ppi_rts);
630+
ret = nrfx_ppi_channel_disable(nordic_nrf5_uart_state[uart_object->instance].ppi_rts);
629631
MBED_ASSERT(ret == NRF_SUCCESS);
630632

631633
/* Free flow control gpiote pin if it was previously set */
632634
if (nordic_nrf5_uart_state[uart_object->instance].rts != NRF_UART_PSEL_DISCONNECTED) {
633-
nrf_drv_gpiote_out_uninit((nrf_drv_gpiote_pin_t)uart_object->rts);
635+
nrfx_gpiote_out_uninit((nrfx_gpiote_pin_t)uart_object->rts);
634636
}
635637

636638
/* Allocate and enable flow control gpiote pin if it is being used */
637639
if (uart_object->rts != NRF_UART_PSEL_DISCONNECTED) {
638640

639-
static const nrf_drv_gpiote_out_config_t config = {
641+
static const nrfx_gpiote_out_config_t config = {
640642
.init_state = NRF_GPIOTE_INITIAL_VALUE_HIGH,
641643
.task_pin = true,
642644
.action = NRF_GPIOTE_POLARITY_LOTOHI
643645
};
644646

645647
/* Allocate gpiote channel */
646-
ret = nrf_drv_gpiote_out_init((nrf_drv_gpiote_pin_t)uart_object->rts, &config);
648+
ret = nrfx_gpiote_out_init((nrfx_gpiote_pin_t)uart_object->rts, &config);
647649
if (ret == NRF_ERROR_INVALID_STATE) {
648650
/* Pin was previously set to GPIO so uninitialize it */
649-
nrf_drv_gpiote_out_uninit((nrf_drv_gpiote_pin_t)uart_object->rts);
650-
ret = nrf_drv_gpiote_out_init((nrf_drv_gpiote_pin_t)uart_object->rts, &config);
651+
nrfx_gpiote_out_uninit((nrfx_gpiote_pin_t)uart_object->rts);
652+
ret = nrfx_gpiote_out_init((nrfx_gpiote_pin_t)uart_object->rts, &config);
651653
}
652654
MBED_ASSERT(ret == NRF_SUCCESS);
653655

654656
/* Set RTS high on the ENDRX event */
655-
ret = nrf_drv_ppi_channel_assign(nordic_nrf5_uart_state[uart_object->instance].ppi_rts,
656-
nrf_uarte_event_address_get(nordic_nrf5_uart_register[uart_object->instance], NRF_UARTE_EVENT_ENDRX),
657-
nrf_drv_gpiote_out_task_addr_get(uart_object->rts));
657+
ret = nrfx_ppi_channel_assign(nordic_nrf5_uart_state[uart_object->instance].ppi_rts,
658+
nrf_uarte_event_address_get(nordic_nrf5_uart_register[uart_object->instance], NRF_UARTE_EVENT_ENDRX),
659+
nrfx_gpiote_out_task_addr_get(uart_object->rts));
658660
MBED_ASSERT(ret == NRF_SUCCESS);
659661

660-
ret = nrf_drv_ppi_channel_enable(nordic_nrf5_uart_state[uart_object->instance].ppi_rts);
662+
ret = nrfx_ppi_channel_enable(nordic_nrf5_uart_state[uart_object->instance].ppi_rts);
661663
MBED_ASSERT(ret == NRF_SUCCESS);
662664

663665
/* Enable gpiote task - rts pin can no longer be used as GPIO at this point */
664-
nrf_drv_gpiote_out_task_enable((nrf_drv_gpiote_pin_t)uart_object->rts);
666+
nrfx_gpiote_out_task_enable((nrfx_gpiote_pin_t)uart_object->rts);
665667
}
666668

667669
nordic_nrf5_uart_state[uart_object->instance].rts = uart_object->rts;
@@ -841,33 +843,11 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
841843
first_init = false;
842844

843845
/* Initialize components that serial relies on. */
844-
nrf_drv_ppi_init();
845-
if (!nrf_drv_gpiote_is_init()) {
846-
nrf_drv_gpiote_init();
846+
// nrf_drv_ppi_init();
847+
if (!nrfx_gpiote_is_init()) {
848+
nrfx_gpiote_init();
847849
}
848850

849-
/* Register RTC2 ISR. */
850-
NVIC_SetVector(RTC2_IRQn, (uint32_t) nordic_nrf5_rtc2_handler);
851-
852-
/* Clear RTC2 channel events. */
853-
nrf_rtc_event_clear(NRF_RTC2, NRF_RTC_EVENT_COMPARE_0);
854-
nrf_rtc_event_clear(NRF_RTC2, NRF_RTC_EVENT_COMPARE_1);
855-
856-
/* Enable interrupts for all four RTC2 channels. */
857-
nrf_rtc_event_enable(NRF_RTC2,
858-
NRF_RTC_INT_COMPARE0_MASK |
859-
NRF_RTC_INT_COMPARE1_MASK);
860-
861-
/* Enable RTC2 IRQ. Priority is set to highest so that the UARTE ISR can't interrupt it. */
862-
NRFX_IRQ_PRIORITY_SET(RTC2_IRQn, APP_IRQ_PRIORITY_HIGHEST);
863-
NRFX_IRQ_ENABLE(RTC2_IRQn);
864-
865-
866-
/* Start RTC2. According to the datasheet the added power consumption is neglible so
867-
* the RTC2 will run forever.
868-
*/
869-
nrf_rtc_task_trigger(NRF_RTC2, NRF_RTC_TASK_START);
870-
871851
/* Enable interrupts for SWI. */
872852
NVIC_SetVector(SWI0_EGU0_IRQn, (uint32_t) nordic_nrf5_uart_swi0);
873853
NRFX_IRQ_PRIORITY_SET(SWI0_EGU0_IRQn, APP_IRQ_PRIORITY_LOWEST);
@@ -881,7 +861,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
881861
nordic_nrf5_uart_state[0].owner = NULL;
882862

883863
/* Allocate a PPI channel for flow control */
884-
ret = nrf_drv_ppi_channel_alloc(&nordic_nrf5_uart_state[0].ppi_rts);
864+
ret = nrfx_ppi_channel_alloc(&nordic_nrf5_uart_state[0].ppi_rts);
885865
MBED_ASSERT(ret == NRF_SUCCESS);
886866

887867
/* Clear RTS */
@@ -959,7 +939,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx)
959939
/* Wait until NRF_UARTE_EVENT_TXDRDY is set before proceeding. */
960940
bool done = false;
961941
do {
962-
done = nrf_uarte_event_extra_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY);
942+
done = nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY);
963943
} while(done == false);
964944
}
965945

@@ -1330,7 +1310,7 @@ int serial_getc(serial_t *obj)
13301310
core_util_atomic_incr_u32(&nordic_nrf5_uart_state[instance].fifo_free_count, 1);
13311311
if (nordic_nrf5_uart_state[instance].rx_suspended) {
13321312
nordic_nrf5_uart_state[instance].rx_suspended = false;
1333-
nrf_drv_gpiote_clr_task_trigger(nordic_nrf5_uart_state[instance].rts);
1313+
nrfx_gpiote_clr_task_trigger(nordic_nrf5_uart_state[instance].rts);
13341314
}
13351315

13361316
return *byte;
@@ -1359,10 +1339,10 @@ void serial_putc(serial_t *obj, int character)
13591339

13601340
/* Wait until UART is ready to send next character. */
13611341
do {
1362-
done = nrf_uarte_event_extra_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY);
1342+
done = nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY);
13631343
} while(done == false);
13641344

1365-
nrf_uarte_event_extra_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY);
1345+
nrf_uarte_event_clear(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY);
13661346

13671347
/* Arm Tx DMA buffer. */
13681348
nordic_nrf5_uart_state[instance].tx_data = character;
@@ -1425,7 +1405,7 @@ int serial_writable(serial_t *obj)
14251405
int instance = uart_object->instance;
14261406

14271407
return ((nordic_nrf5_uart_state[instance].tx_in_progress == 0) &&
1428-
(nrf_uarte_event_extra_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY)));
1408+
(nrf_uarte_event_check(nordic_nrf5_uart_register[instance], NRF_UARTE_EVENT_TXDRDY)));
14291409
}
14301410

14311411
/***

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