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Merge pull request #12949 from 0xc0170/feature_CMSIS_5_b5f0603d6
CMSIS: update to CMSIS 5.7.0
2 parents 595754d + ac3df20 commit e371db4

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‎cmsis/TARGET_CORTEX_A/cmsis_armcc.h

Lines changed: 8 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file cmsis_armcc.h
33
* @brief CMSIS compiler specific macros, functions, instructions
4-
* @version V1.0.3
5-
* @date 15. May 2019
4+
* @version V1.0.4
5+
* @date 30. July 2019
66
******************************************************************************/
77
/*
88
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
@@ -86,6 +86,9 @@
8686
#ifndef __PACKED
8787
#define __PACKED __attribute__((packed))
8888
#endif
89+
#ifndef __COMPILER_BARRIER
90+
#define __COMPILER_BARRIER() __memory_changed()
91+
#endif
8992

9093
/* ########################## Core Instruction Access ######################### */
9194
/**
@@ -111,29 +114,17 @@
111114
/**
112115
\brief Instruction Synchronization Barrier
113116
*/
114-
#define __ISB() do {\
115-
__schedule_barrier();\
116-
__isb(0xF);\
117-
__schedule_barrier();\
118-
} while (0U)
117+
#define __ISB() __isb(0xF)
119118

120119
/**
121120
\brief Data Synchronization Barrier
122121
*/
123-
#define __DSB() do {\
124-
__schedule_barrier();\
125-
__dsb(0xF);\
126-
__schedule_barrier();\
127-
} while (0U)
122+
#define __DSB() __dsb(0xF)
128123

129124
/**
130125
\brief Data Memory Barrier
131126
*/
132-
#define __DMB() do {\
133-
__schedule_barrier();\
134-
__dmb(0xF);\
135-
__schedule_barrier();\
136-
} while (0U)
127+
#define __DMB() __dmb(0xF)
137128

138129
/**
139130
\brief Reverse byte order (32 bit)

‎cmsis/TARGET_CORTEX_A/cmsis_armclang.h

Lines changed: 76 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/**************************************************************************//**
22
* @file cmsis_armclang.h
33
* @brief CMSIS compiler specific macros, functions, instructions
4-
* @version V1.1.1
5-
* @date 15. May 2019
4+
* @version V1.2.0
5+
* @date 05. August 2019
66
******************************************************************************/
77
/*
88
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
@@ -102,6 +102,9 @@
102102
#ifndef __PACKED
103103
#define __PACKED __attribute__((packed))
104104
#endif
105+
#ifndef __COMPILER_BARRIER
106+
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
107+
#endif
105108

106109
/* ########################## Core Instruction Access ######################### */
107110
/**
@@ -127,29 +130,17 @@
127130
/**
128131
\brief Instruction Synchronization Barrier
129132
*/
130-
#define __ISB() do {\
131-
__schedule_barrier();\
132-
__builtin_arm_isb(0xF);\
133-
__schedule_barrier();\
134-
} while (0U)
133+
#define __ISB() __builtin_arm_isb(0xF)
135134

136135
/**
137136
\brief Data Synchronization Barrier
138137
*/
139-
#define __DSB() do {\
140-
__schedule_barrier();\
141-
__builtin_arm_dsb(0xF);\
142-
__schedule_barrier();\
143-
} while (0U)
138+
#define __DSB() __builtin_arm_dsb(0xF)
144139

145140
/**
146141
\brief Data Memory Barrier
147142
*/
148-
#define __DMB() do {\
149-
__schedule_barrier();\
150-
__builtin_arm_dmb(0xF);\
151-
__schedule_barrier();\
152-
} while (0U)
143+
#define __DMB() __builtin_arm_dmb(0xF)
153144

154145
/**
155146
\brief Reverse byte order (32 bit)
@@ -311,6 +302,73 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
311302
*/
312303
#define __USAT __builtin_arm_usat
313304

305+
/* ################### Compiler specific Intrinsics ########################### */
306+
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
307+
Access to dedicated SIMD instructions
308+
@{
309+
*/
310+
311+
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
312+
313+
#define __SADD8 __builtin_arm_sadd8
314+
#define __SADD16 __builtin_arm_sadd16
315+
#define __QADD8 __builtin_arm_qadd8
316+
#define __QSUB8 __builtin_arm_qsub8
317+
#define __QADD16 __builtin_arm_qadd16
318+
#define __SHADD16 __builtin_arm_shadd16
319+
#define __QSUB16 __builtin_arm_qsub16
320+
#define __SHSUB16 __builtin_arm_shsub16
321+
#define __QASX __builtin_arm_qasx
322+
#define __SHASX __builtin_arm_shasx
323+
#define __QSAX __builtin_arm_qsax
324+
#define __SHSAX __builtin_arm_shsax
325+
#define __SXTB16 __builtin_arm_sxtb16
326+
#define __SMUAD __builtin_arm_smuad
327+
#define __SMUADX __builtin_arm_smuadx
328+
#define __SMLAD __builtin_arm_smlad
329+
#define __SMLADX __builtin_arm_smladx
330+
#define __SMLALD __builtin_arm_smlald
331+
#define __SMLALDX __builtin_arm_smlaldx
332+
#define __SMUSD __builtin_arm_smusd
333+
#define __SMUSDX __builtin_arm_smusdx
334+
#define __SMLSDX __builtin_arm_smlsdx
335+
#define __USAT16 __builtin_arm_usat16
336+
#define __SSUB8 __builtin_arm_ssub8
337+
#define __SXTB16 __builtin_arm_sxtb16
338+
#define __SXTAB16 __builtin_arm_sxtab16
339+
340+
341+
__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
342+
{
343+
int32_t result;
344+
345+
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
346+
return(result);
347+
}
348+
349+
__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
350+
{
351+
int32_t result;
352+
353+
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
354+
return(result);
355+
}
356+
357+
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
358+
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
359+
360+
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
361+
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
362+
363+
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
364+
{
365+
int32_t result;
366+
367+
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
368+
return(result);
369+
}
370+
371+
#endif /* (__ARM_FEATURE_DSP == 1) */
314372

315373
/* ########################### Core Function Access ########################### */
316374

@@ -343,7 +401,7 @@ __STATIC_FORCEINLINE uint32_t __get_CPSR(void)
343401
*/
344402
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
345403
{
346-
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
404+
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
347405
}
348406

349407
/** \brief Get Mode

‎cmsis/TARGET_CORTEX_A/cmsis_compiler.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,10 @@
9898
#ifndef __PACKED
9999
#define __PACKED __attribute__((packed))
100100
#endif
101+
#ifndef __COMPILER_BARRIER
102+
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
103+
#define __COMPILER_BARRIER() (void)0
104+
#endif
101105

102106

103107
/*
@@ -144,6 +148,10 @@
144148
#ifndef __PACKED
145149
#define __PACKED __packed__
146150
#endif
151+
#ifndef __COMPILER_BARRIER
152+
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
153+
#define __COMPILER_BARRIER() (void)0
154+
#endif
147155

148156

149157
/*
@@ -190,6 +198,10 @@
190198
#ifndef __PACKED
191199
#define __PACKED @packed
192200
#endif
201+
#ifndef __COMPILER_BARRIER
202+
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
203+
#define __COMPILER_BARRIER() (void)0
204+
#endif
193205

194206

195207
#else

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