RTX - update to v4.79 for Cortex-M

Changes to the original kernel:

Cortex-M requires to define __CMSIS_OS_RTX, and __MBED_CMSIS_RTOS_CM. The macro __MBED_CMSIS_RTOS_CM
is mbed specific macro, to track changes to the kernel. This should keep us aware what has changed. For instance,
one breaking change was thread adding instances variable, which were not in mbed. This can be find as
it's protected via __MBED_CMSIS_RTOS_CM ifdef.

```
// added for mbed compatibility
// original RTX code
```

Startup for toolchains - mbed defines own stack pointer (set_main_stack()), therefore it should be called in the startup.
IAR added low level init calls and dynamic intialization to the IAR startup. All defined in RTX_CM_lib.h.

The timer thread has task id 0x01, main task 0x02. There are exception for main task not to check for
overflows. This is mbed specific, was reapplied from mbed code base.

IAR fixed SVC calls, this fix had to be reapplied (repo mbed PR 736 for more information).

Author: 0xc0170

core/mbed-rtos/rtx/TARGET_CORTEX_M/HAL_CM.c

@@ -1,12 +1,12 @@
 /*----------------------------------------------------------------------------
- *      RL-ARM - RTX
+ *      CMSIS-RTOS  -  RTX
  *----------------------------------------------------------------------------
  *      Name:    HAL_CM.C
  *      Purpose: Hardware Abstraction Layer for Cortex-M
- *      Rev.:    V4.60
+ *      Rev.:    V4.79
  *----------------------------------------------------------------------------
  *
- * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
  * All rights reserved.
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
  *---------------------------------------------------------------------------*/
 
 #include "rt_TypeDef.h"
-#include "RTX_Conf.h"
+#include "RTX_Config.h"
 #include "rt_HAL_CM.h"
 
 
@@ -58,12 +58,15 @@ void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
 
   /* Prepare a complete interrupt frame for first task start */
   size = p_TCB->priv_stack >> 2;
+  if (size == 0U) {
+    size = (U16)os_stackinfo >> 2;
+  }
 
   /* Write to the top of stack. */
   stk = &p_TCB->stack[size];
 
   /* Auto correct to 8-byte ARM stack alignment. */
-  if ((U32)stk & 0x04) {
+  if ((U32)stk & 0x04U) {
     stk--;
   }
 
@@ -74,8 +77,8 @@ void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
   stk[14] = (U32)task_body;
 
   /* Clear R4-R11,R0-R3,R12,LR registers. */
-  for (i = 0; i < 14; i++) {
-    stk[i] = 0;
+  for (i = 0U; i < 14U; i++) {
+    stk[i] = 0U;
   }
 
   /* Assign a void pointer to R0. */
@@ -87,31 +90,50 @@ void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
   /* Task entry point. */
   p_TCB->ptask = task_body;
 
+  /* Initialize stack with magic pattern. */
+  if (os_stackinfo & 0x10000000U) {
+    if (size > (16U+1U)) {
+      for (i = ((size - 16U)/2U) - 1U; i; i--) {
+        stk -= 2U;
+        stk[1] = MAGIC_PATTERN;
+        stk[0] = MAGIC_PATTERN;
+      }
+      if (--stk > p_TCB->stack) {
+        *stk = MAGIC_PATTERN;
+      }
+    }
+  }
+
+#ifdef __MBED_CMSIS_RTOS_CM
   /* Set a magic word for checking of stack overflow.
-   For the main thread (ID: 0x01) the stack is in a memory area shared with the
+   For the main thread (ID: 0x02) the stack is in a memory area shared with the
    heap, therefore the last word of the stack is a moving target.
    We want to do stack/heap collision detection instead.
   */
-  if (p_TCB->task_id != 0x01)
+  if (p_TCB->task_id != 0x02)
       p_TCB->stack[0] = MAGIC_WORD;
+#else
+  /* Set a magic word for checking of stack overflow. */
+  p_TCB->stack[0] = MAGIC_WORD;
+#endif
 }
 
 
 /*--------------------------- rt_ret_val ----------------------------------*/
 
 static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
   /* Get pointer to task return value registers (R0..R3) in Stack */
-#if (__TARGET_FPU_VFP)
+#if defined(__TARGET_FPU_VFP)
   if (p_TCB->stack_frame) {
     /* Extended Stack Frame: R4-R11,S16-S31,R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR */
-    return (U32 *)(p_TCB->tsk_stack + 8*4 + 16*4);
+    return (U32 *)(p_TCB->tsk_stack + (8U*4U) + (16U*4U));
   } else {
     /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
-    return (U32 *)(p_TCB->tsk_stack + 8*4);
+    return (U32 *)(p_TCB->tsk_stack + (8U*4U));
   }
 #else
   /* Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
-  return (U32 *)(p_TCB->tsk_stack + 8*4);
+  return (U32 *)(p_TCB->tsk_stack + (8U*4U));
 #endif
 }
 
@@ -135,9 +157,9 @@ void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
 
 #ifdef DBG_MSG
 void dbg_init (void) {
-  if ((DEMCR & DEMCR_TRCENA)     &&
-      (ITM_CONTROL & ITM_ITMENA) &&
-      (ITM_ENABLE & (1UL << 31))) {
+  if (((DEMCR & DEMCR_TRCENA) != 0U)     && 
+      ((ITM_CONTROL & ITM_ITMENA) != 0U) &&
+      ((ITM_ENABLE & (1UL << 31)) != 0U)) {
     dbg_msg = __TRUE;
   }
 }
@@ -147,24 +169,22 @@ void dbg_init (void) {
 
 #ifdef DBG_MSG
 void dbg_task_notify (P_TCB p_tcb, BOOL create) {
-  while (ITM_PORT31_U32 == 0);
+  while (ITM_PORT31_U32 == 0U);
   ITM_PORT31_U32 = (U32)p_tcb->ptask;
-  while (ITM_PORT31_U32 == 0);
-  ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
+  while (ITM_PORT31_U32 == 0U);
+  ITM_PORT31_U16 = (U16)((create << 8) | p_tcb->task_id);
 }
 #endif
 
 /*--------------------------- dbg_task_switch -------------------------------*/
 
 #ifdef DBG_MSG
 void dbg_task_switch (U32 task_id) {
-  while (ITM_PORT31_U32 == 0);
-  ITM_PORT31_U8 = task_id;
+  while (ITM_PORT31_U32 == 0U);
+  ITM_PORT31_U8 = (U8)task_id;
 }
 #endif
 
-
 /*----------------------------------------------------------------------------
  * end of file
  *---------------------------------------------------------------------------*/
-