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Fix for Issue#1740. The latest SDK drivers for FTM & TPM has the fix for this issue
This fixes issues seen when running FTM and TPM demos in certain modes Signed-off-by: Mahadevan Mahesh <[email protected]>
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6 files changed

+213
-92
lines changed

6 files changed

+213
-92
lines changed

‎libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.c

Lines changed: 38 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -237,11 +237,8 @@ status_t FTM_Init(FTM_Type *base, const ftm_config_t *config)
237237
/* Configure the update mechanism for buffered registers */
238238
FTM_SetPwmSync(base, config->pwmSyncMode);
239239

240-
if (config->reloadPoints)
241-
{
242-
/* Setup intermediate register reload points */
243-
FTM_SetReloadPoints(base, config->reloadPoints);
244-
}
240+
/* Setup intermediate register reload points */
241+
FTM_SetReloadPoints(base, config->reloadPoints);
245242

246243
/* Set the clock prescale factor */
247244
base->SC = FTM_SC_PS(config->prescale);
@@ -327,6 +324,9 @@ status_t FTM_SetupPwm(FTM_Type *base,
327324
uint32_t srcClock_Hz)
328325
{
329326
assert(chnlParams);
327+
assert(srcClock_Hz);
328+
assert(pwmFreq_Hz);
329+
assert(numOfChnls);
330330

331331
uint32_t mod, reg;
332332
uint32_t ftmClock = (srcClock_Hz / (1U << (base->SC & FTM_SC_PS_MASK)));
@@ -373,7 +373,7 @@ status_t FTM_SetupPwm(FTM_Type *base,
373373
reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
374374

375375
/* Setup the active level */
376-
reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level));
376+
reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT);
377377

378378
/* Edge-aligned mode needs MSB to be 1, don't care for Center-aligned mode */
379379
reg |= FTM_CnSC_MSB(1U);
@@ -397,6 +397,10 @@ status_t FTM_SetupPwm(FTM_Type *base,
397397
}
398398

399399
base->CONTROLS[chnlParams->chnlNumber].CnV = cnv;
400+
#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
401+
/* Set to output mode */
402+
FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true);
403+
#endif
400404
}
401405
else
402406
{
@@ -445,7 +449,7 @@ status_t FTM_SetupPwm(FTM_Type *base,
445449
reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
446450

447451
/* Setup the active level for channel n */
448-
reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level));
452+
reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT);
449453

450454
/* Update the mode and edge level for channel n */
451455
base->CONTROLS[chnlParams->chnlNumber * 2].CnSC = reg;
@@ -455,25 +459,25 @@ status_t FTM_SetupPwm(FTM_Type *base,
455459
reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
456460

457461
/* Setup the active level for channel n + 1 */
458-
reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level));
462+
reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT);
459463

460464
/* Update the mode and edge level for channel n + 1*/
461465
base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC = reg;
462466

463-
/* Set the channel pair values */
464-
base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge;
465-
base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv;
466-
467467
/* Set the combine bit for the channel pair */
468468
base->COMBINE |=
469469
(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlParams->chnlNumber)));
470-
}
470+
471+
/* Set the channel pair values */
472+
base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge;
473+
base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv;
471474

472475
#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
473-
/* Set to output mode */
474-
FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true);
476+
/* Set to output mode */
477+
FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2), true);
478+
FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2 + 1), true);
475479
#endif
476-
480+
}
477481
chnlParams++;
478482
}
479483

@@ -535,6 +539,13 @@ void FTM_SetupInputCapture(FTM_Type *base,
535539
{
536540
uint32_t reg;
537541

542+
/* Clear the combine bit for the channel pair */
543+
base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
544+
/* Clear the dual edge capture mode because it's it's higher priority */
545+
base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
546+
/* Clear the quadrature decoder mode beacause it's higher priority */
547+
base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK;
548+
538549
reg = base->CONTROLS[chnlNumber].CnSC;
539550
reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
540551
reg |= captureMode;
@@ -562,15 +573,22 @@ void FTM_SetupOutputCompare(FTM_Type *base,
562573
{
563574
uint32_t reg;
564575

565-
/* Set output on match to the requested level */
566-
base->CONTROLS[chnlNumber].CnV = compareValue;
576+
/* Clear the combine bit for the channel pair */
577+
base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
578+
/* Clear the dual edge capture mode because it's it's higher priority */
579+
base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
580+
/* Clear the quadrature decoder mode beacause it's higher priority */
581+
base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK;
567582

568583
reg = base->CONTROLS[chnlNumber].CnSC;
569584
reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
570585
reg |= compareMode;
571586
/* Setup the channel output behaviour when a match occurs with the compare value */
572587
base->CONTROLS[chnlNumber].CnSC = reg;
573588

589+
/* Set output on match to the requested level */
590+
base->CONTROLS[chnlNumber].CnV = compareValue;
591+
574592
#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
575593
/* Set to output mode */
576594
FTM_SetPwmOutputEnable(base, chnlNumber, true);
@@ -662,6 +680,8 @@ void FTM_SetupQuadDecode(FTM_Type *base,
662680

663681
void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams)
664682
{
683+
assert(faultParams);
684+
665685
uint32_t reg;
666686

667687
reg = base->FLTCTRL;

‎libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K22F/drivers/fsl_ftm.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@
3333
#include "fsl_common.h"
3434

3535
/*!
36-
* @addtogroup ftm_driver
36+
* @addtogroup ftm
3737
* @{
3838
*/
3939

@@ -162,7 +162,7 @@ typedef struct _ftm_phase_param
162162
typedef struct _ftm_fault_param
163163
{
164164
bool enableFaultInput; /*!< True: Fault input is enabled; false: Fault input is disabled */
165-
bool faultLevel; /*!< True: Fault polarity is active low i.e '0' indicates a fault;
165+
bool faultLevel; /*!< True: Fault polarity is active low i.e., '0' indicates a fault;
166166
False: Fault polarity is active high */
167167
bool useFaultFilter; /*!< True: Use the filtered fault signal;
168168
False: Use the direct path from fault input */

‎libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.c

Lines changed: 38 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -237,11 +237,8 @@ status_t FTM_Init(FTM_Type *base, const ftm_config_t *config)
237237
/* Configure the update mechanism for buffered registers */
238238
FTM_SetPwmSync(base, config->pwmSyncMode);
239239

240-
if (config->reloadPoints)
241-
{
242-
/* Setup intermediate register reload points */
243-
FTM_SetReloadPoints(base, config->reloadPoints);
244-
}
240+
/* Setup intermediate register reload points */
241+
FTM_SetReloadPoints(base, config->reloadPoints);
245242

246243
/* Set the clock prescale factor */
247244
base->SC = FTM_SC_PS(config->prescale);
@@ -327,6 +324,9 @@ status_t FTM_SetupPwm(FTM_Type *base,
327324
uint32_t srcClock_Hz)
328325
{
329326
assert(chnlParams);
327+
assert(srcClock_Hz);
328+
assert(pwmFreq_Hz);
329+
assert(numOfChnls);
330330

331331
uint32_t mod, reg;
332332
uint32_t ftmClock = (srcClock_Hz / (1U << (base->SC & FTM_SC_PS_MASK)));
@@ -373,7 +373,7 @@ status_t FTM_SetupPwm(FTM_Type *base,
373373
reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
374374

375375
/* Setup the active level */
376-
reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level));
376+
reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT);
377377

378378
/* Edge-aligned mode needs MSB to be 1, don't care for Center-aligned mode */
379379
reg |= FTM_CnSC_MSB(1U);
@@ -397,6 +397,10 @@ status_t FTM_SetupPwm(FTM_Type *base,
397397
}
398398

399399
base->CONTROLS[chnlParams->chnlNumber].CnV = cnv;
400+
#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
401+
/* Set to output mode */
402+
FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true);
403+
#endif
400404
}
401405
else
402406
{
@@ -445,7 +449,7 @@ status_t FTM_SetupPwm(FTM_Type *base,
445449
reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
446450

447451
/* Setup the active level for channel n */
448-
reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level));
452+
reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT);
449453

450454
/* Update the mode and edge level for channel n */
451455
base->CONTROLS[chnlParams->chnlNumber * 2].CnSC = reg;
@@ -455,25 +459,25 @@ status_t FTM_SetupPwm(FTM_Type *base,
455459
reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
456460

457461
/* Setup the active level for channel n + 1 */
458-
reg |= (FTM_CnSC_ELSA(chnlParams->level) | FTM_CnSC_ELSB(chnlParams->level));
462+
reg |= (uint32_t)(chnlParams->level << FTM_CnSC_ELSA_SHIFT);
459463

460464
/* Update the mode and edge level for channel n + 1*/
461465
base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnSC = reg;
462466

463-
/* Set the channel pair values */
464-
base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge;
465-
base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv;
466-
467467
/* Set the combine bit for the channel pair */
468468
base->COMBINE |=
469469
(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * chnlParams->chnlNumber)));
470-
}
470+
471+
/* Set the channel pair values */
472+
base->CONTROLS[chnlParams->chnlNumber * 2].CnV = cnvFirstEdge;
473+
base->CONTROLS[(chnlParams->chnlNumber * 2) + 1].CnV = cnvFirstEdge + cnv;
471474

472475
#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
473-
/* Set to output mode */
474-
FTM_SetPwmOutputEnable(base, chnlParams->chnlNumber, true);
476+
/* Set to output mode */
477+
FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2), true);
478+
FTM_SetPwmOutputEnable(base, (ftm_chnl_t)((uint8_t)chnlParams->chnlNumber * 2 + 1), true);
475479
#endif
476-
480+
}
477481
chnlParams++;
478482
}
479483

@@ -535,6 +539,13 @@ void FTM_SetupInputCapture(FTM_Type *base,
535539
{
536540
uint32_t reg;
537541

542+
/* Clear the combine bit for the channel pair */
543+
base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
544+
/* Clear the dual edge capture mode because it's it's higher priority */
545+
base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
546+
/* Clear the quadrature decoder mode beacause it's higher priority */
547+
base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK;
548+
538549
reg = base->CONTROLS[chnlNumber].CnSC;
539550
reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
540551
reg |= captureMode;
@@ -562,15 +573,22 @@ void FTM_SetupOutputCompare(FTM_Type *base,
562573
{
563574
uint32_t reg;
564575

565-
/* Set output on match to the requested level */
566-
base->CONTROLS[chnlNumber].CnV = compareValue;
576+
/* Clear the combine bit for the channel pair */
577+
base->COMBINE &= ~(1U << (FTM_COMBINE_COMBINE0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
578+
/* Clear the dual edge capture mode because it's it's higher priority */
579+
base->COMBINE &= ~(1U << (FTM_COMBINE_DECAPEN0_SHIFT + (FTM_COMBINE_COMBINE1_SHIFT * (chnlNumber >> 1))));
580+
/* Clear the quadrature decoder mode beacause it's higher priority */
581+
base->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK;
567582

568583
reg = base->CONTROLS[chnlNumber].CnSC;
569584
reg &= ~(FTM_CnSC_MSA_MASK | FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK);
570585
reg |= compareMode;
571586
/* Setup the channel output behaviour when a match occurs with the compare value */
572587
base->CONTROLS[chnlNumber].CnSC = reg;
573588

589+
/* Set output on match to the requested level */
590+
base->CONTROLS[chnlNumber].CnV = compareValue;
591+
574592
#if defined(FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT) && (FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT)
575593
/* Set to output mode */
576594
FTM_SetPwmOutputEnable(base, chnlNumber, true);
@@ -662,6 +680,8 @@ void FTM_SetupQuadDecode(FTM_Type *base,
662680

663681
void FTM_SetupFault(FTM_Type *base, ftm_fault_input_t faultNumber, const ftm_fault_param_t *faultParams)
664682
{
683+
assert(faultParams);
684+
665685
uint32_t reg;
666686

667687
reg = base->FLTCTRL;

‎libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KSDK2_MCUS/TARGET_K64F/drivers/fsl_ftm.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@
3333
#include "fsl_common.h"
3434

3535
/*!
36-
* @addtogroup ftm_driver
36+
* @addtogroup ftm
3737
* @{
3838
*/
3939

@@ -162,7 +162,7 @@ typedef struct _ftm_phase_param
162162
typedef struct _ftm_fault_param
163163
{
164164
bool enableFaultInput; /*!< True: Fault input is enabled; false: Fault input is disabled */
165-
bool faultLevel; /*!< True: Fault polarity is active low i.e '0' indicates a fault;
165+
bool faultLevel; /*!< True: Fault polarity is active low i.e., '0' indicates a fault;
166166
False: Fault polarity is active high */
167167
bool useFaultFilter; /*!< True: Use the filtered fault signal;
168168
False: Use the direct path from fault input */

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