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Add XIP capability, enable QSPI. XIP can be enable by adding macro XIP_ENABLE in mbed_app.json. It's disabled by default.
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-26
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7 files changed

+191
-26
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‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/device/TOOLCHAIN_GCC_ARM/startup_psoc6_01_cm4.S

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@@ -53,23 +53,6 @@ __StackLimit:
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__StackTop:
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.size __StackTop, . - __StackTop
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56-
.section .heap
57-
.align 3
58-
#ifdef __HEAP_SIZE
59-
.equ Heap_Size, __HEAP_SIZE
60-
#else
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.equ Heap_Size, 0x00000400
62-
#endif
63-
.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
72-
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.section .vectors
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.align 2
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.globl __Vectors

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h

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@@ -22,6 +22,76 @@
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* limitations under the License.
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********************************************************************************/
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/*******************************************************************************
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QSPI_CONFIG_START
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<CySMIFConfiguration>
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<DevicePath>PSoC 6.xml</DevicePath>
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<SlotConfigs>
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<SlotConfig>
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<SlaveSlot>0</SlaveSlot>
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<PartNumber>S25FL512S</PartNumber>
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<MemoryMapped>true</MemoryMapped>
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<DualQuad>None</DualQuad>
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<StartAddress>0x18000000</StartAddress>
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<Size>0x40000</Size>
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<EndAddress>0x1803FFFF</EndAddress>
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<WriteEnable>true</WriteEnable>
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<Encrypt>false</Encrypt>
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<DataSelect>QUAD_SPI_DATA_0_3</DataSelect>
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<MemoryConfigsPath>S25FL512S</MemoryConfigsPath>
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<ConfigDataInFlash>true</ConfigDataInFlash>
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</SlotConfig>
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<SlotConfig>
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<SlaveSlot>1</SlaveSlot>
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<PartNumber>Not used</PartNumber>
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<MemoryMapped>false</MemoryMapped>
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<DualQuad>None</DualQuad>
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<StartAddress>0x18010000</StartAddress>
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<Size>0x10000</Size>
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<EndAddress>0x1801FFFF</EndAddress>
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<WriteEnable>false</WriteEnable>
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<Encrypt>false</Encrypt>
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<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
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<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
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<ConfigDataInFlash>false</ConfigDataInFlash>
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</SlotConfig>
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<SlotConfig>
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<SlaveSlot>2</SlaveSlot>
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<PartNumber>Not used</PartNumber>
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<MemoryMapped>false</MemoryMapped>
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<DualQuad>None</DualQuad>
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<StartAddress>0x18020000</StartAddress>
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<Size>0x10000</Size>
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<EndAddress>0x1802FFFF</EndAddress>
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<WriteEnable>false</WriteEnable>
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<Encrypt>false</Encrypt>
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<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
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<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
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<ConfigDataInFlash>false</ConfigDataInFlash>
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</SlotConfig>
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<SlotConfig>
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<SlaveSlot>3</SlaveSlot>
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<PartNumber>Not used</PartNumber>
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<MemoryMapped>false</MemoryMapped>
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<DualQuad>None</DualQuad>
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<StartAddress>0x18030000</StartAddress>
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<Size>0x10000</Size>
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<EndAddress>0x1803FFFF</EndAddress>
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<WriteEnable>false</WriteEnable>
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<Encrypt>false</Encrypt>
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<DataSelect>SPI_MOSI_MISO_DATA_0_1</DataSelect>
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<MemoryConfigsPath>default_memory.xml</MemoryConfigsPath>
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<ConfigDataInFlash>false</ConfigDataInFlash>
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</SlotConfig>
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</SlotConfigs>
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</CySMIFConfiguration>
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QSPI_CONFIG_END
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*******************************************************************************/
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2595
#ifndef CYCFG_QSPI_MEMSLOT_H
2696
#define CYCFG_QSPI_MEMSLOT_H
2797
#include "cy_smif_memslot.h"
@@ -41,6 +111,7 @@ extern const cy_stc_smif_mem_cmd_t S25FL128S_SlaveSlot_0_writeStsRegQeCmd;
41111
extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL128S_SlaveSlot_0;
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43113
extern const cy_stc_smif_mem_config_t S25FL128S_SlaveSlot_0;
114+
44115
extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM];
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46117
extern const cy_stc_smif_block_config_t smifBlockConfig;

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_064_SB/device/TOOLCHAIN_GCC_ARM/cyb06xx7_cm4_dual.ld

Lines changed: 23 additions & 9 deletions
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@@ -162,6 +162,21 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
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SECTIONS
163163
{
164164
/* Cortex-M4 application image */
165+
/* Places the code in the Execute in Place (XIP) section. See the smif driver
166+
* documentation for details.
167+
*/
168+
.cy_xip :
169+
{
170+
. = ALIGN(4);
171+
__cy_xip_start__ = .;
172+
KEEP(*(.cy_xip))
173+
#if XIP_ENABLE == 1
174+
*lwipstack*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
175+
*mbed-cloud-client*.o (.text .text* .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
176+
#endif
177+
__cy_xip_end__ = .;
178+
} > xip
179+
165180
.text FLASH_CM4_START :
166181
{
167182
. = ALIGN(4);
@@ -173,7 +188,11 @@ SECTIONS
173188
__end__ = .;
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175190
. = ALIGN(4);
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#if XIP_ENABLE == 1
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*(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .text .text*)
193+
#else
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*(.text*)
195+
#endif
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178197
KEEP(*(.init))
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KEEP(*(.fini))
@@ -193,7 +212,11 @@ SECTIONS
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*(.dtors)
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195214
/* Read-only code (constants). */
215+
#if XIP_ENABLE == 1
216+
*(EXCLUDE_FILE(*lwipstack*.o *mbed-cloud-client*.o) .rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
217+
#else
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*(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*)
219+
#endif
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198221
KEEP(*(.eh_frame*))
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} > flash
@@ -400,15 +423,6 @@ SECTIONS
400423
} > sflash_rtoc_2
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402425

403-
/* Places the code in the Execute in Place (XIP) section. See the smif driver
404-
* documentation for details.
405-
*/
406-
.cy_xip :
407-
{
408-
KEEP(*(.cy_xip))
409-
} > xip
410-
411-
412426
/* eFuse */
413427
.cy_efuse :
414428
{

‎targets/TARGET_Cypress/TARGET_PSOC6/mbed_overrides.c

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@@ -31,6 +31,9 @@
3131
void mailbox_init(void);
3232
#endif
3333

34+
#if defined(XIP_ENABLE)
35+
extern void qspi_xip_start();
36+
#endif
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3538
#if (defined(CY_CFG_PWR_SYS_IDLE_MODE) && (CY_CFG_PWR_SYS_IDLE_MODE == CY_CFG_PWR_MODE_ACTIVE))
3639
/*******************************************************************************
@@ -100,6 +103,9 @@ void mbed_sdk_init(void)
100103
/* Enable global interrupts (disabled in CM4 startup assembly) */
101104
__enable_irq();
102105
#endif
106+
#if defined(XIP_ENABLE)
107+
qspi_xip_start();
108+
#endif
103109

104110
#if defined (CY_CFG_PWR_SYS_IDLE_MODE)
105111
/* Configure the lowest power state the system is allowed to enter

‎targets/TARGET_Cypress/TARGET_PSOC6/xip_user.c

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@@ -0,0 +1,84 @@
1+
/* mbed Microcontroller Library
2+
* Copyright (c) 2019, Arm Limited and affiliates.
3+
* SPDX-License-Identifier: Apache-2.0
4+
*
5+
* Licensed under the Apache License, Version 2.0 (the "License");
6+
* you may not use this file except in compliance with the License.
7+
* You may obtain a copy of the License at
8+
*
9+
* http://www.apache.org/licenses/LICENSE-2.0
10+
*
11+
* Unless required by applicable law or agreed to in writing, software
12+
* distributed under the License is distributed on an "AS IS" BASIS,
13+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14+
* See the License for the specific language governing permissions and
15+
* limitations under the License.
16+
*/
17+
18+
#ifdef XIP_ENABLE
19+
#include "cy_smif.h"
20+
#include "cy_smif_memslot.h"
21+
#include "cycfg_qspi_memslot.h"
22+
#include "qspi_api.h"
23+
24+
/********************************************************************
25+
* NULL terminated array of SMIF structures for use in TOC2
26+
********************************************************************/
27+
typedef struct
28+
{
29+
const cy_stc_smif_block_config_t * smifCfg; /* Pointer to SMIF top-level configuration */
30+
const uint32_t null_t; /* NULL termination */
31+
} stc_smif_ipblocks_arr_t;
32+
33+
/*
34+
* PSoC 6 boot sequence is such that the TOC2 needs to verified before switching to the application code.
35+
* In the mbed build system the CRC for TOC2 is not calculated. Hence CRC has to be manually placed in the TOC2
36+
* SMIF config structure is placed at a fixed address so as to fix the CRC for table of contents2 (TOC2).
37+
*/
38+
__attribute__((section(".cy_sflash_user_data"))) __attribute__((used))
39+
const stc_smif_ipblocks_arr_t smifIpBlocksArr = {&smifBlockConfig, 0x00000000};
40+
41+
/********************************************************************
42+
* Point to the SMIF block structure in the table of contents2 (TOC2).
43+
*
44+
* This enables memory reads using Cypress Programmer, without this
45+
* structure, external memory access from Cypress Programmer will not
46+
* work
47+
********************************************************************/
48+
49+
__attribute__((section(".cy_toc_part2"))) __attribute__((used))
50+
const int cyToc[128] =
51+
{
52+
0x200-4, /* Offset=0x00: Object Size, bytes */
53+
0x01211220, /* Offset=0x04: Magic Number (TOC Part 2, ID) */
54+
0, /* Offset=0x08: Key Storage Address */
55+
(int)&smifIpBlocksArr, /* Offset=0x0C: This points to a null terminated array of SMIF structures. */
56+
0x10000000u, /* Offset=0x10: App image start address */
57+
[127] = 0x0B1F0000 /* Offset=0x1FC: CRC16-CCITT (the upper 2 bytes contain the CRC and the lower 2 bytes are 0) */
58+
};
59+
60+
/* QSPI HAL object */
61+
qspi_t QSPI_HW;
62+
63+
void qspi_xip_start()
64+
{
65+
QSPI_HW.hal_qspi.base = SMIF0;
66+
QSPI_HW.hal_qspi.slave_select = CY_SMIF_SLAVE_SELECT_0;
67+
qspi_status_t qspi_api_result = QSPI_STATUS_OK;
68+
69+
/* Initialize the QSPI interface */
70+
qspi_api_result = qspi_init(&QSPI_HW, QSPI_IO_0, QSPI_IO_1, QSPI_IO_2, QSPI_IO_3, QSPI_CLK, QSPI_SEL, 0, 0);
71+
72+
if(qspi_api_result == QSPI_STATUS_OK)
73+
{
74+
/* Initialize the memory device connected to SMIF slot */
75+
Cy_SMIF_Memslot_Init(QSPI_HW.hal_qspi.base, (cy_stc_smif_block_config_t*)&smifBlockConfig, &(QSPI_HW.hal_qspi.context));
76+
77+
/* Enable quad mode of operation */
78+
Cy_SMIF_Memslot_QuadEnable(QSPI_HW.hal_qspi.base, (cy_stc_smif_mem_config_t*)smifMemConfigs[0], &(QSPI_HW.hal_qspi.context));
79+
80+
/* Set the operation mode to XIP */
81+
Cy_SMIF_SetMode(QSPI_HW.hal_qspi.base, CY_SMIF_MEMORY);
82+
}
83+
}
84+
#endif

‎targets/targets.json

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@@ -8579,6 +8579,7 @@
85798579
"SERIAL_FC",
85808580
"SERIAL_ASYNCH",
85818581
"SLEEP",
8582+
"QSPI",
85828583
"SPI",
85838584
"SPI_ASYNCH",
85848585
"SPISLAVE",

‎tools/toolchains/mbed_toolchain.py

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@@ -990,6 +990,12 @@ def add_linker_defines(self):
990990
self.ld.append(define_string)
991991
self.flags["ld"].append(define_string)
992992

993+
if "XIP_ENABLE" in self.target.macros :
994+
define_string = self.make_ld_define(
995+
"XIP_ENABLE", 1)
996+
self.ld.append(define_string)
997+
self.flags["ld"].append(define_string)
998+
993999
# Set the configuration data
9941000
def set_config_data(self, config_data):
9951001
self.config_data = config_data

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