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M263: Fix redundant SPI clock generation
Fix SPI clocks are generated redundantly at the end of transfer. This is also to fix FPGA CI test mbed_hal_fpga_ci_test_shield-spi/ SPI - async mode.
1 parent d15abe5 commit eb435b7

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2 files changed

+7
-10
lines changed

2 files changed

+7
-10
lines changed

targets/TARGET_NUVOTON/TARGET_M261/objects.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -85,7 +85,7 @@ struct spi_s {
8585
int dma_chn_id_tx;
8686
int dma_chn_id_rx;
8787
uint32_t event;
88-
uint32_t hdlr_async;
88+
uint32_t txrx_rmn; // Track tx/rx frames remaining in interrupt way
8989
};
9090

9191
struct i2c_s {

targets/TARGET_NUVOTON/TARGET_M261/spi_api.c

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -388,6 +388,9 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
388388

389389
SPI_ENABLE_SYNC(spi_base);
390390

391+
// Initialize total SPI transfer frames
392+
obj->spi.txrx_rmn = NU_MAX(tx_length, rx_length);
393+
391394
if (obj->spi.dma_usage == DMA_USAGE_NEVER) {
392395
// Interrupt way
393396
spi_master_write_asynch(obj, spi_fifo_depth(obj) / 2);
@@ -658,16 +661,12 @@ static uint32_t spi_event_check(spi_t *obj)
658661
static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
659662
{
660663
uint32_t n_words = 0;
661-
uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
662-
uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
663-
uint32_t max_tx = NU_MAX(tx_rmn, rx_rmn);
664-
max_tx = NU_MIN(max_tx, tx_limit);
665664
uint8_t data_width = spi_get_data_width(obj);
666665
uint8_t bytes_per_word = (data_width + 7) / 8;
667666
uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
668667
SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
669668

670-
while ((n_words < max_tx) && spi_writeable(obj)) {
669+
while (obj->spi.txrx_rmn && spi_writeable(obj)) {
671670
if (spi_is_tx_complete(obj)) {
672671
// Transmit dummy as transmit buffer is empty
673672
SPI_WRITE_TX(spi_base, 0);
@@ -690,6 +689,7 @@ static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
690689
obj->tx_buff.pos ++;
691690
}
692691
n_words ++;
692+
obj->spi.txrx_rmn --;
693693
}
694694

695695
//Return the number of words that have been sent
@@ -710,15 +710,12 @@ static uint32_t spi_master_write_asynch(spi_t *obj, uint32_t tx_limit)
710710
static uint32_t spi_master_read_asynch(spi_t *obj)
711711
{
712712
uint32_t n_words = 0;
713-
uint32_t tx_rmn = obj->tx_buff.length - obj->tx_buff.pos;
714-
uint32_t rx_rmn = obj->rx_buff.length - obj->rx_buff.pos;
715-
uint32_t max_rx = NU_MAX(tx_rmn, rx_rmn);
716713
uint8_t data_width = spi_get_data_width(obj);
717714
uint8_t bytes_per_word = (data_width + 7) / 8;
718715
uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
719716
SPI_T *spi_base = (SPI_T *) NU_MODBASE(obj->spi.spi);
720717

721-
while ((n_words < max_rx) && spi_readable(obj)) {
718+
while (spi_readable(obj)) {
722719
if (spi_is_rx_complete(obj)) {
723720
// Disregard as receive buffer is full
724721
SPI_READ_RX(spi_base);

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