Skip to content

Commit ec8dd1d

Browse files
0xc01700xc0170
committed
Merge pull request #972 from bcostm/master
NUCLEO_L073RZ - Add new target
2 parents 33b8d29 + 5af36d1 commit ec8dd1d

File tree

52 files changed

+13381
-9
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

52 files changed

+13381
-9
lines changed

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/startup_stm32l073xx.s

Lines changed: 252 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,252 @@
1+
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
2+
;* File Name : startup_stm32l073xx.s
3+
;* Author : MCD Application Team
4+
;* Version : V1.2.0
5+
;* Date : 06-February-2015
6+
;* Description : STM32l073xx Devices vector table for MDK-ARM toolchain.
7+
;* This module performs:
8+
;* - Set the initial SP
9+
;* - Set the initial PC == Reset_Handler
10+
;* - Set the vector table entries with the exceptions ISR address
11+
;* - Branches to __main in the C library (which eventually
12+
;* calls main()).
13+
;* After Reset the Cortex-M0+ processor is in Thread mode,
14+
;* priority is Privileged, and the Stack is set to Main.
15+
;* <<< Use Configuration Wizard in Context Menu >>>
16+
;*******************************************************************************
17+
;*
18+
;* Redistribution and use in source and binary forms, with or without modification,
19+
;* are permitted provided that the following conditions are met:
20+
;* 1. Redistributions of source code must retain the above copyright notice,
21+
;* this list of conditions and the following disclaimer.
22+
;* 2. Redistributions in binary form must reproduce the above copyright notice,
23+
;* this list of conditions and the following disclaimer in the documentation
24+
;* and/or other materials provided with the distribution.
25+
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
26+
;* may be used to endorse or promote products derived from this software
27+
;* without specific prior written permission.
28+
;*
29+
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
30+
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
31+
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32+
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
33+
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34+
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35+
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
36+
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
37+
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38+
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39+
;*
40+
;*******************************************************************************
41+
;
42+
; Amount of memory (in bytes) allocated for Stack
43+
; Tailor this value to your application needs
44+
; <h> Stack Configuration
45+
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
46+
; </h>
47+
48+
Stack_Size EQU 0x00000400
49+
50+
AREA STACK, NOINIT, READWRITE, ALIGN=3
51+
EXPORT __initial_sp
52+
53+
Stack_Mem SPACE Stack_Size
54+
__initial_sp EQU 0x20005000 ; Top of RAM
55+
56+
57+
; <h> Heap Configuration
58+
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
59+
; </h>
60+
61+
Heap_Size EQU 0x00000400
62+
63+
AREA HEAP, NOINIT, READWRITE, ALIGN=3
64+
EXPORT __heap_base
65+
EXPORT __heap_limit
66+
67+
__heap_base
68+
Heap_Mem SPACE Heap_Size
69+
__heap_limit EQU (__initial_sp - Stack_Size)
70+
71+
PRESERVE8
72+
THUMB
73+
74+
75+
; Vector Table Mapped to Address 0 at Reset
76+
AREA RESET, DATA, READONLY
77+
EXPORT __Vectors
78+
EXPORT __Vectors_End
79+
EXPORT __Vectors_Size
80+
81+
__Vectors DCD __initial_sp ; Top of Stack
82+
DCD Reset_Handler ; Reset Handler
83+
DCD NMI_Handler ; NMI Handler
84+
DCD HardFault_Handler ; Hard Fault Handler
85+
DCD 0 ; Reserved
86+
DCD 0 ; Reserved
87+
DCD 0 ; Reserved
88+
DCD 0 ; Reserved
89+
DCD 0 ; Reserved
90+
DCD 0 ; Reserved
91+
DCD 0 ; Reserved
92+
DCD SVC_Handler ; SVCall Handler
93+
DCD DebugMon_Handler ; Debug Monitor Handler
94+
DCD 0 ; Reserved
95+
DCD PendSV_Handler ; PendSV Handler
96+
DCD SysTick_Handler ; SysTick Handler
97+
98+
; External Interrupts
99+
DCD WWDG_IRQHandler ; Window Watchdog
100+
DCD PVD_IRQHandler ; PVD through EXTI Line detect
101+
DCD RTC_IRQHandler ; RTC through EXTI Line
102+
DCD FLASH_IRQHandler ; FLASH
103+
DCD RCC_CRS_IRQHandler ; RCC and CRS
104+
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
105+
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
106+
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
107+
DCD TSC_IRQHandler ; TSC
108+
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
109+
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
110+
DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
111+
DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
112+
DCD LPTIM1_IRQHandler ; LPTIM1
113+
DCD USART4_5_IRQHandler ; USART4 and USART5
114+
DCD TIM2_IRQHandler ; TIM2
115+
DCD TIM3_IRQHandler ; TIM3
116+
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
117+
DCD TIM7_IRQHandler ; TIM7
118+
DCD 0 ; Reserved
119+
DCD TIM21_IRQHandler ; TIM21
120+
DCD I2C3_IRQHandler ; I2C3
121+
DCD TIM22_IRQHandler ; TIM22
122+
DCD I2C1_IRQHandler ; I2C1
123+
DCD I2C2_IRQHandler ; I2C2
124+
DCD SPI1_IRQHandler ; SPI1
125+
DCD SPI2_IRQHandler ; SPI2
126+
DCD USART1_IRQHandler ; USART1
127+
DCD USART2_IRQHandler ; USART2
128+
DCD RNG_LPUART1_IRQHandler ; RNG and LPUART1
129+
DCD LCD_IRQHandler ; LCD
130+
DCD USB_IRQHandler ; USB
131+
132+
__Vectors_End
133+
134+
__Vectors_Size EQU __Vectors_End - __Vectors
135+
136+
AREA |.text|, CODE, READONLY
137+
138+
; Reset handler routine
139+
Reset_Handler PROC
140+
EXPORT Reset_Handler [WEAK]
141+
IMPORT __main
142+
IMPORT SystemInit
143+
LDR R0, =SystemInit
144+
BLX R0
145+
LDR R0, =__main
146+
BX R0
147+
ENDP
148+
149+
; Dummy Exception Handlers (infinite loops which can be modified)
150+
151+
NMI_Handler PROC
152+
EXPORT NMI_Handler [WEAK]
153+
B .
154+
ENDP
155+
HardFault_Handler\
156+
PROC
157+
EXPORT HardFault_Handler [WEAK]
158+
B .
159+
ENDP
160+
SVC_Handler PROC
161+
EXPORT SVC_Handler [WEAK]
162+
B .
163+
ENDP
164+
DebugMon_Handler\
165+
PROC
166+
EXPORT DebugMon_Handler [WEAK]
167+
B .
168+
ENDP
169+
PendSV_Handler PROC
170+
EXPORT PendSV_Handler [WEAK]
171+
B .
172+
ENDP
173+
SysTick_Handler PROC
174+
EXPORT SysTick_Handler [WEAK]
175+
B .
176+
ENDP
177+
178+
Default_Handler PROC
179+
180+
EXPORT WWDG_IRQHandler [WEAK]
181+
EXPORT PVD_IRQHandler [WEAK]
182+
EXPORT RTC_IRQHandler [WEAK]
183+
EXPORT FLASH_IRQHandler [WEAK]
184+
EXPORT RCC_CRS_IRQHandler [WEAK]
185+
EXPORT EXTI0_1_IRQHandler [WEAK]
186+
EXPORT EXTI2_3_IRQHandler [WEAK]
187+
EXPORT EXTI4_15_IRQHandler [WEAK]
188+
EXPORT TSC_IRQHandler [WEAK]
189+
EXPORT DMA1_Channel1_IRQHandler [WEAK]
190+
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
191+
EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
192+
EXPORT ADC1_COMP_IRQHandler [WEAK]
193+
EXPORT LPTIM1_IRQHandler [WEAK]
194+
EXPORT USART4_5_IRQHandler [WEAK]
195+
EXPORT TIM2_IRQHandler [WEAK]
196+
EXPORT TIM3_IRQHandler [WEAK]
197+
EXPORT TIM6_DAC_IRQHandler [WEAK]
198+
EXPORT TIM7_IRQHandler [WEAK]
199+
EXPORT TIM21_IRQHandler [WEAK]
200+
EXPORT TIM22_IRQHandler [WEAK]
201+
EXPORT I2C1_IRQHandler [WEAK]
202+
EXPORT I2C2_IRQHandler [WEAK]
203+
EXPORT I2C3_IRQHandler [WEAK]
204+
EXPORT SPI1_IRQHandler [WEAK]
205+
EXPORT SPI2_IRQHandler [WEAK]
206+
EXPORT USART1_IRQHandler [WEAK]
207+
EXPORT USART2_IRQHandler [WEAK]
208+
EXPORT RNG_LPUART1_IRQHandler [WEAK]
209+
EXPORT LCD_IRQHandler [WEAK]
210+
EXPORT USB_IRQHandler [WEAK]
211+
212+
213+
WWDG_IRQHandler
214+
PVD_IRQHandler
215+
RTC_IRQHandler
216+
FLASH_IRQHandler
217+
RCC_CRS_IRQHandler
218+
EXTI0_1_IRQHandler
219+
EXTI2_3_IRQHandler
220+
EXTI4_15_IRQHandler
221+
TSC_IRQHandler
222+
DMA1_Channel1_IRQHandler
223+
DMA1_Channel2_3_IRQHandler
224+
DMA1_Channel4_5_6_7_IRQHandler
225+
ADC1_COMP_IRQHandler
226+
LPTIM1_IRQHandler
227+
USART4_5_IRQHandler
228+
TIM2_IRQHandler
229+
TIM3_IRQHandler
230+
TIM6_DAC_IRQHandler
231+
TIM7_IRQHandler
232+
TIM21_IRQHandler
233+
TIM22_IRQHandler
234+
I2C1_IRQHandler
235+
I2C2_IRQHandler
236+
I2C3_IRQHandler
237+
SPI1_IRQHandler
238+
SPI2_IRQHandler
239+
USART1_IRQHandler
240+
USART2_IRQHandler
241+
RNG_LPUART1_IRQHandler
242+
LCD_IRQHandler
243+
USB_IRQHandler
244+
245+
B .
246+
247+
ENDP
248+
249+
ALIGN
250+
END
251+
252+
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
; Scatter-Loading Description File
2+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3+
; Copyright (c) 2015, STMicroelectronics
4+
; All rights reserved.
5+
;
6+
; Redistribution and use in source and binary forms, with or without
7+
; modification, are permitted provided that the following conditions are met:
8+
;
9+
; 1. Redistributions of source code must retain the above copyright notice,
10+
; this list of conditions and the following disclaimer.
11+
; 2. Redistributions in binary form must reproduce the above copyright notice,
12+
; this list of conditions and the following disclaimer in the documentation
13+
; and/or other materials provided with the distribution.
14+
; 3. Neither the name of STMicroelectronics nor the names of its contributors
15+
; may be used to endorse or promote products derived from this software
16+
; without specific prior written permission.
17+
;
18+
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19+
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20+
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21+
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
22+
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23+
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24+
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25+
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26+
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27+
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
29+
30+
; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
31+
LR_IROM1 0x08000000 0x10000 { ; load region size_region
32+
33+
ER_IROM1 0x08000000 0x30000 { ; load address = execution address
34+
*.o (RESET, +First)
35+
*(InRoot$$Sections)
36+
.ANY (+RO)
37+
}
38+
39+
; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
40+
RW_IRAM1 (0x20000000+0xC0) (0x5000-0xC0) { ; RW data
41+
.ANY (+RW +ZI)
42+
}
43+
44+
}
45+

‎libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/sys.cpp

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,56 @@
1+
/* mbed Microcontroller Library - stackheap
2+
* Setup a fixed single stack/heap memory model,
3+
* between the top of the RW/ZI region and the stackpointer
4+
*******************************************************************************
5+
* Copyright (c) 2014, STMicroelectronics
6+
* All rights reserved.
7+
*
8+
* Redistribution and use in source and binary forms, with or without
9+
* modification, are permitted provided that the following conditions are met:
10+
*
11+
* 1. Redistributions of source code must retain the above copyright notice,
12+
* this list of conditions and the following disclaimer.
13+
* 2. Redistributions in binary form must reproduce the above copyright notice,
14+
* this list of conditions and the following disclaimer in the documentation
15+
* and/or other materials provided with the distribution.
16+
* 3. Neither the name of STMicroelectronics nor the names of its contributors
17+
* may be used to endorse or promote products derived from this software
18+
* without specific prior written permission.
19+
*
20+
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21+
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22+
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
23+
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
24+
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25+
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
26+
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
27+
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
28+
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29+
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30+
*******************************************************************************
31+
*/
32+
33+
#ifdef __cplusplus
34+
extern "C" {
35+
#endif
36+
37+
#include <rt_misc.h>
38+
#include <stdint.h>
39+
40+
extern char Image$$RW_IRAM1$$ZI$$Limit[];
41+
42+
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
43+
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
44+
uint32_t sp_limit = __current_sp();
45+
46+
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
47+
48+
struct __initial_stackheap r;
49+
r.heap_base = zi_limit;
50+
r.heap_limit = sp_limit;
51+
return r;
52+
}
53+
54+
#ifdef __cplusplus
55+
}
56+
#endif

0 commit comments

Comments
 (0)