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Add RTC and Sleep to CM3DS
This commit represents the second stage of the low power implementations that are required from Mbed 5.10 onwards. Besides the default hal implementations (rtc_api.c and sleep.c), the PL031 RTC's native driver needed to be added. Due to HW limitations in SSE-050 and the CM3DS, Deep Sleep couldn't be implemented, therefore it is functionally identical to Sleep (WFI). Change-Id: Ibed2bdb452f48c98024dc7ef07fb51a4425e0a80 Signed-off-by: Bence Kaposzta <[email protected]>
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‎targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/device_cfg.h

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@@ -49,7 +49,8 @@
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*/
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#define USEC_TIMER_BIT_WIDTH 32U
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#define USEC_REPORTED_SHIFT 5U
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#define USEC_REPORTED_FREQ_HZ (TIMERS_INPUT_CLOCK_FREQ_HZ >> USEC_REPORTED_SHIFT)
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#define USEC_REPORTED_FREQ_HZ (TIMERS_INPUT_CLOCK_FREQ_HZ >> \
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USEC_REPORTED_SHIFT)
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#define USEC_REPORTED_BITS (USEC_TIMER_BIT_WIDTH - USEC_REPORTED_SHIFT)
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/* mbed low power ticker configuration */
@@ -72,6 +73,9 @@
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(LP_TIMER_HW_PRESCALER+LP_REPORTED_SHIFT))
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#define LP_REPORTED_BITS (LP_TIMER_BIT_WIDTH - LP_REPORTED_SHIFT)
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/* RTC PL031 */
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#define RTC_PL031
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/* ARM GPIO */
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#define ARM_GPIO0
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#define ARM_GPIO1

‎targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/rtc_pl031_drv.c

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/*
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* Copyright (c) 2018 Arm Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* \file rtc_pl031_drv.c
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* \brief Implementation of the PL031 Real Time Clock (RTC) native driver.
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*
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* \note PL031 device specific definitions based on
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* real_time_clock_pl031_r1p3_technical_reference_manual.pdf
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* which is available from http://infocenter.arm.com.
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*/
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#include <stddef.h>
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#include "rtc_pl031_drv.h"
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/**
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* \brief Structure to access the memory mapped registers of the PL031.
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*/
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struct rtc_pl031_dev_reg_map_t {
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volatile uint32_t rtcdr; /*!< Data Register */
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volatile uint32_t rtcmr; /*!< Match Register */
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volatile uint32_t rtclr; /*!< Load Register */
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volatile uint32_t rtccr; /*!< Control Register */
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volatile uint32_t rtcimsc;
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/*!< Interrupt Mask Set or Clear Register */
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volatile uint32_t rtcris; /*!< Raw Interrupt Status Register */
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volatile uint32_t rtcmis; /*!< Masked Interrupt Status Register */
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volatile uint32_t rtcicr; /*!< Interrupt Clear Register */
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volatile uint32_t reserved[1008]; /*!< Reserved from Offset 0x20-0xFDC */
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volatile uint32_t rtcperiphid0; /*!< Peripheral ID0 Register */
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volatile uint32_t rtcperiphid1; /*!< Peripheral ID1 Register */
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volatile uint32_t rtcperiphid2; /*!< Peripheral ID2 Register */
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volatile uint32_t rtcperiphid3; /*!< Peripheral ID3 Register */
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volatile uint32_t rtcpcellid0; /*!< Primary Cell ID0 Register */
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volatile uint32_t rtcpcellid1; /*!< Primary Cell ID1 Register */
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volatile uint32_t rtcpcellid2; /*!< Primary Cell ID2 Register */
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volatile uint32_t rtcpcellid3; /*!< Primary Cell ID3 Register */
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};
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/* RTC Control Register */
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#define RTC_PL031_RTCCR_ENABLE_POS 0x0U
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#define RTC_PL031_RTCCR_ENABLE_MSK (0x1U << RTC_PL031_RTCCR_ENABLE_POS)
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/* RTC Interrupt Mask Set or Clear Register */
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#define RTC_PL031_RTCIMSC_SET_CLEAR_POS 0x0U
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#define RTC_PL031_RTCIMSC_SET_CLEAR_MSK (0x1U << \
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RTC_PL031_RTCIMSC_SET_CLEAR_POS)
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/* RTC RAW Interrupt Status Register */
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#define RTC_PL031_RTCRIS_STATUS_POS 0x0U
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#define RTC_PL031_RTCRIS_STATUS_MSK (0x1U << RTC_PL031_RTCRIS_STATUS_POS)
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/* RTC Masked Interrupt Status Register */
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#define RTC_PL031_RTCMIS_STATUS_POS 0x0U
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#define RTC_PL031_RTCMIS_STATUS_MSK (0x1U << RTC_PL031_RTCMIS_STATUS_POS)
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/* RTC Interrupt Clear Register */
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#define RTC_PL031_RTCICR_CLEAR_POS 0x0U
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#define RTC_PL031_RTCICR_CLEAR_MSK (0x1U << RTC_PL031_RTCICR_CLEAR_POS)
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bool rtc_pl031_init(struct rtc_pl031_dev_t* dev)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc;
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if (dev == NULL) {
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return false;
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}
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p_rtc = (struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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p_rtc->rtcmr = 0U;
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p_rtc->rtcicr = RTC_PL031_RTCICR_CLEAR_MSK;
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return true;
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}
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bool rtc_pl031_dev_enable(struct rtc_pl031_dev_t* dev)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc;
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if (dev == NULL) {
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return false;
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}
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p_rtc = (struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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p_rtc->rtccr = RTC_PL031_RTCCR_ENABLE_MSK;
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return true;
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}
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bool rtc_pl031_dev_disable(struct rtc_pl031_dev_t* dev)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc;
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if (dev == NULL) {
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return false;
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}
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p_rtc = (struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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p_rtc->rtccr = 0U;
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return true;
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}
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bool rtc_pl031_read_current_time(struct rtc_pl031_dev_t* dev, uint32_t *seconds)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc;
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if (dev == NULL || seconds == NULL) {
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return false;
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}
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p_rtc = (struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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*seconds = (uint32_t)p_rtc->rtcdr;
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return true;
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}
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bool rtc_pl031_write_current_time(struct rtc_pl031_dev_t* dev, uint32_t seconds)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc;
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if (dev == NULL) {
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return false;
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}
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p_rtc = (struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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p_rtc->rtclr = (uint32_t)seconds;
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return true;
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}
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bool rtc_pl031_enable_interrupt(struct rtc_pl031_dev_t* dev)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc;
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if (dev == NULL) {
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return false;
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}
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p_rtc = (struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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p_rtc->rtcimsc = 0U;
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return true;
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}
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bool rtc_pl031_disable_interrupt(struct rtc_pl031_dev_t* dev)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc;
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if (dev == NULL) {
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return false;
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}
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p_rtc = (struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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p_rtc->rtcimsc = RTC_PL031_RTCIMSC_SET_CLEAR_MSK;
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return true;
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}
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bool rtc_pl031_is_interrupt_masked(struct rtc_pl031_dev_t* dev)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc =
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(struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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if (p_rtc->rtcimsc & RTC_PL031_RTCIMSC_SET_CLEAR_MSK){
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return true;
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} else {
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return false;
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}
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}
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bool rtc_pl031_is_raw_interrupt_pending(struct rtc_pl031_dev_t* dev)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc =
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(struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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if (p_rtc->rtcris & RTC_PL031_RTCRIS_STATUS_MSK) {
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return true;
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} else {
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return false;
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}
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}
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bool rtc_pl031_is_masked_interrupt_pending(struct rtc_pl031_dev_t* dev)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc =
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(struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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if (p_rtc->rtcmis & RTC_PL031_RTCMIS_STATUS_MSK) {
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return true;
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} else {
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return false;
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}
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}
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bool rtc_pl031_write_match_value(struct rtc_pl031_dev_t* dev, uint32_t seconds)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc;
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if (dev == NULL) {
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return false;
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}
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p_rtc = (struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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p_rtc->rtcmr = (uint32_t)seconds;
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return true;
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}
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bool rtc_pl031_clear_interrupt(struct rtc_pl031_dev_t* dev)
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{
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struct rtc_pl031_dev_reg_map_t* p_rtc;
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if (dev == NULL) {
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return false;
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}
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p_rtc = (struct rtc_pl031_dev_reg_map_t*) dev->cfg->base;
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p_rtc->rtcicr = RTC_PL031_RTCICR_CLEAR_MSK;
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return true;
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}

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