NUCLEO_WB55RG: update STM common files

- Include RTC ll file from hal as in other families
- STM32WB: update Flash API driver

Author: bcostm

targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/stm32wbxx.h

@@ -62,7 +62,7 @@
    In this case, these drivers will not be included and the application code will
    be based on direct access to peripherals registers
    */
-  /*#define USE_HAL_DRIVER */
+  #define USE_HAL_DRIVER
 #endif /* USE_HAL_DRIVER */
 
 /**
@@ -84,7 +84,7 @@
 /** @addtogroup Device_Included
   * @{
   */
-
+#define STM32WB55xx // Added for MBED
 #if defined(STM32WB55xx)
   #include "stm32wb55xx.h"
 #else

targets/TARGET_STM/TARGET_STM32WB/device.h

@@ -37,4 +37,6 @@
 /*  WORKAROUND waiting for mbed-os issue 4408 to be addressed */
 #include "stm32wbxx_ll_usart.h"
 
+#include "stm32wbxx_ll_rtc.h"
+
 #endif

targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_conf.h

@@ -200,6 +200,10 @@
   * @brief Include module's header file
   */
 
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32wbxx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
 #ifdef HAL_ADC_MODULE_ENABLED
   #include "stm32wbxx_hal_adc.h"
 #endif /* HAL_ADC_MODULE_ENABLED */
@@ -220,10 +224,6 @@
   #include "stm32wbxx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32wbxx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
 #ifdef HAL_EXTI_MODULE_ENABLED
   #include "stm32wbxx_hal_exti.h"
 #endif /* HAL_EXTI_MODULE_ENABLED */

targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_rtc.h

@@ -27,6 +27,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32wbxx_hal_def.h"
+#include "stm32wbxx_ll_rtc.h"
 
 /* Include low level driver */
 #include "stm32wbxx_ll_exti.h"

targets/TARGET_STM/TARGET_STM32WB/flash_api.c

@@ -207,4 +207,11 @@ uint32_t flash_get_size(const flash_t *obj) {
     return FLASH_SIZE;
 }
 
+uint8_t flash_get_erase_value(const flash_t *obj)
+{
+    (void)obj;
+
+    return 0xFF;
+}
+
 #endif

targets/TARGET_STM/gpio_irq_api.c

@@ -194,7 +194,9 @@ int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32
     }
 
     /* Enable SYSCFG Clock */
+#if !defined(TARGET_STM32WB)
     __HAL_RCC_SYSCFG_CLK_ENABLE();
+#endif
 
     uint32_t port_index  = STM_PORT(pin);
     uint32_t pin_index  = STM_PIN(pin);

targets/TARGET_STM/serial_api.c

@@ -568,12 +568,12 @@ HAL_StatusTypeDef init_uart(serial_t *obj)
 #if defined(LPUART1_BASE)
     if (huart->Instance == LPUART1) {
         if (obj_s->baudrate <= 9600) {
-#if ((MBED_CONF_TARGET_LPUART_CLOCK_SOURCE) & USE_LPUART_CLK_LSE) && !TARGET_STM32H7
+#if ((MBED_CONF_TARGET_LPUART_CLOCK_SOURCE) & USE_LPUART_CLK_LSE) && !TARGET_STM32H7 && !TARGET_STM32WB
             HAL_UARTEx_EnableClockStopMode(huart);
 #endif
             HAL_UARTEx_EnableStopMode(huart);
         } else {
-#if !TARGET_STM32H7
+#if (!defined(TARGET_STM32H7) && !defined(TARGET_STM32WB))
             HAL_UARTEx_DisableClockStopMode(huart);
 #endif
             HAL_UARTEx_DisableStopMode(huart);

targets/TARGET_STM/trng_api.c

@@ -37,6 +37,8 @@ void trng_init(trng_t *obj)
         error("Only 1 RNG instance supported\r\n");
     }
 
+#if !defined(TARGET_STM32WB)
+/*  Because M0 core of WB also needs RG RNG is already clocked by default */
 #if defined(RCC_PERIPHCLK_RNG)
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
 
@@ -51,6 +53,7 @@ void trng_init(trng_t *obj)
         error("RNG clock configuration error\n");
     }
 #endif
+#endif //!defined(TARGET_STM32WB)
 
     /* RNG Peripheral clock enable */
     __HAL_RCC_RNG_CLK_ENABLE();