add hal-qspi test

Author: maciejbocianski

TESTS/mbed_hal/qspi/flash_configs/MX25R6435F_config.h

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+/* mbed Microcontroller Library
+ * Copyright (c) 2018-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_QSPI_FLASH_MX25R6435F_H
+#define MBED_QSPI_FLASH_MX25R6435F_H
+
+
+#define QSPI_FLASH_CHIP_STRING "MX25R6435F"
+
+// Command for reading status register
+#define QSPI_CMD_RDSR                           0x05
+// Command for reading configuration register
+#define QSPI_CMD_RDCR                           0x15
+// Command for writing status/configuration register
+#define QSPI_CMD_WRSR                           0x01
+// Command for reading security register
+#define QSPI_CMD_RDSCUR                         0x2B
+
+// Command for setting Reset Enable
+#define QSPI_CMD_RSTEN                          0x66
+// Command for setting Reset
+#define QSPI_CMD_RST                            0x99
+
+// Command for setting write enable
+#define QSPI_CMD_WREN                           0x06
+// Command for setting write disable
+#define QSPI_CMD_WRDI                           0x04
+
+// WRSR operations max time [us] (datasheet max time + 15%)
+#define QSPI_WRSR_MAX_TIME                      34500   // 30ms
+// general wait max time [us]
+#define QSPI_WAIT_MAX_TIME                      10000   // 100ms
+
+
+// Commands for writing (page programming)
+#define QSPI_CMD_WRITE_1IO                      0x02    // 1-1-1 mode
+#define QSPI_CMD_WRITE_4IO                      0x38    // 1-4-4 mode
+
+// write operations max time [us] (datasheet max time + 15%)
+#define QSPI_PAGE_PROG_MAX_TIME                 11500   // 10ms
+
+#define QSPI_PAGE_SIZE                          256     // 256B
+
+// Commands for reading
+#define QSPI_CMD_READ_1IO_FAST                  0x0B   // 1-1-1 mode
+#define QSPI_CMD_READ_1IO                       0x03   // 1-1-1 mode
+#define QSPI_CMD_READ_2IO                       0xBB   // 1-2-2 mode
+#define QSPI_CMD_READ_1I2O                      0x3B   // 1-1-2 mode
+#define QSPI_CMD_READ_4IO                       0xEB   // 1-4-4 mode
+#define QSPI_CMD_READ_1I4O                      0x6B   // 1-1-4 mode
+
+#define QSPI_READ_1IO_DUMMY_CYCLE               0
+#define QSPI_READ_FAST_DUMMY_CYCLE              8
+#define QSPI_READ_2IO_DUMMY_CYCLE               4
+#define QSPI_READ_1I2O_DUMMY_CYCLE              8
+#define QSPI_READ_4IO_DUMMY_CYCLE               6
+#define QSPI_READ_1I4O_DUMMY_CYCLE              8
+
+// Commands for erasing
+#define QSPI_CMD_ERASE_SECTOR                   0x20    // 4kB
+#define QSPI_CMD_ERASE_BLOCK_32                 0x52    // 32kB
+#define QSPI_CMD_ERASE_BLOCK_64                 0xD8    // 64kB
+#define QSPI_CMD_ERASE_CHIP                     0x60    // or 0xC7
+
+// erase operations max time [us] (datasheet max time + 15%)
+#define QSPI_ERASE_SECTOR_MAX_TIME              276000      // 240 ms
+#define QSPI_ERASE_BLOCK_32_MAX_TIME            3000000     // 3s
+#define QSPI_ERASE_BLOCK_64_MAX_TIME            3500000     // 3.5s
+
+// max frequency for basic rw operation
+#define QSPI_COMMON_MAX_FREQUENCY               32000000
+
+#define QSPI_STATUS_REGISTER_SIZE               1
+#define QSPI_CONFIGURATION_REGISTER_SIZE        2
+#define QSPI_SECURITY_REGISTER_SIZE             1
+
+// status register
+#define STATUS_BIT_WIP   (1 << 0)   // write in progress bit
+#define STATUS_BIT_WEL   (1 << 1)   // write enable latch
+#define STATUS_BIT_BP0   (1 << 2)   //
+#define STATUS_BIT_BP1   (1 << 3)   //
+#define STATUS_BIT_BP2   (1 << 4)   //
+#define STATUS_BIT_BP3   (1 << 5)   //
+#define STATUS_BIT_QE    (1 << 6)   // Quad Enable
+#define STATUS_BIT_SRWD  (1 << 7)   // status register write protect
+
+// configuration register 0
+// bit 0, 1, 2, 4, 5, 7 reserved
+#define CONFIG0_BIT_TB   (1 << 3)   // Top/Bottom area protect
+#define CONFIG0_BIT_DC   (1 << 6)   // Dummy Cycle
+
+// configuration register 1
+// bit 0, 2, 3, 4, 5, 6, 7 reserved
+#define CONFIG1_BIT_LH   (1 << 1)   // 0 = Ultra Low power mode, 1 = High performance mode
+
+
+#endif // MBED_QSPI_FLASH_MX25R6435F_H

TESTS/mbed_hal/qspi/flash_configs/NORDIC/NRF52840_DK/flash_config.h

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+/* mbed Microcontroller Library
+ * Copyright (c) 2018-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_QSPI_FLASH_CONFIG_H
+#define MBED_QSPI_FLASH_CONFIG_H
+
+#include "../../MX25R6435F_config.h"
+
+// NRF doesn't uses read/write opcodes, instead it uses commands id's.
+// Before sending it to H/W opcodes are mapped to id's in Mbed hal qspi implementation
+//
+// for more details see:
+// targets\TARGET_NORDIC\TARGET_NRF5x\TARGET_SDK_14_2\device\nrf52840_bitfields.h
+// targets\TARGET_NORDIC\TARGET_NRF5x\qspi_api.c
+
+// NRF doesn't support read 1IO (opcode 0x03)
+#undef QSPI_CMD_READ_1IO
+#define QSPI_CMD_READ_1IO                         QSPI_CMD_READ_1IO_FAST
+
+
+#endif // MBED_QSPI_FLASH_CONFIG_H

TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_L475VG_IOT01A/flash_config.h

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+/* mbed Microcontroller Library
+ * Copyright (c) 2018-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_QSPI_FLASH_CONFIG_H
+#define MBED_QSPI_FLASH_CONFIG_H
+
+#include "../../MX25R6435F_config.h"
+
+// TODO: remove when fixed
+// when perform 4IO write, when memory indicates write finish (changing WIP bit in status register)
+// but actually write is still in progress and we have to wait a bit more before reading
+#define STM_DISCO_L475VG_IOT01A_WRITE_4IO_BUG_WORKAROUND
+
+#endif // MBED_QSPI_FLASH_CONFIG_H

TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

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+/* mbed Microcontroller Library
+ * Copyright (c) 2018-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_FLASH_CONFIGS_H
+#define MBED_FLASH_CONFIGS_H
+
+#if defined(TARGET_DISCO_L475VG_IOT01A)
+#include "STM/DISCO_L475VG_IOT01A/flash_config.h"
+#elif defined(TARGET_NRF52840)
+#include "NORDIC/NRF52840_DK/flash_config.h"
+#endif
+
+#endif // MBED_FLASH_CONFIGS_H