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Merge pull request #9766 from deepikabhavnani/uarm_fixes
Update Toolchain Arm Micro scatter files
2 parents 596b9f7 + 1225499 commit f559d03

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190 files changed

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‎platform/mbed_retarget.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -907,13 +907,14 @@ extern "C" long PREFIX(_flen)(FILEHANDLE fh)
907907
// Do not compile this code for TFM secure target
908908
#if !defined(COMPONENT_SPE) || !defined(TARGET_TFM)
909909

910+
#if !defined(__MICROLIB)
910911
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
911912
__asm(".global __use_two_region_memory\n\t");
912913
__asm(".global __use_no_semihosting\n\t");
913-
914914
#else
915915
#pragma import(__use_two_region_memory)
916916
#endif
917+
#endif
917918

918919
#if !defined(HEAP_START)
919920
// Heap here is considered starting after ZI ends to Stack start
@@ -938,12 +939,14 @@ extern "C" MBED_WEAK __value_in_regs struct __initial_stackheap _mbed_user_setup
938939
return r;
939940
}
940941

942+
#if !defined(__MICROLIB)
941943
extern "C" __value_in_regs struct __argc_argv $Super$$__rt_lib_init(unsigned heapbase, unsigned heaptop);
942944

943945
extern "C" __value_in_regs struct __argc_argv $Sub$$__rt_lib_init(unsigned heapbase, unsigned heaptop)
944946
{
945947
return $Super$$__rt_lib_init((unsigned)HEAP_START, (unsigned)HEAP_LIMIT);
946948
}
949+
#endif
947950

948951
extern "C" __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3)
949952
{

‎rtos/TARGET_CORTEX/TOOLCHAIN_ARM_MICRO/mbed_boot_arm_micro.c

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -16,18 +16,16 @@
1616
*/
1717
#include <stdlib.h>
1818
#include <string.h>
19+
#include <stdint.h>
1920

2021
#include "mbed_boot.h"
2122
#include "mbed_assert.h"
2223

23-
/* Symbols that are typically defined in startup_<mcu>.S */
24-
extern uint32_t __initial_sp[];
25-
extern uint32_t __heap_base[];
26-
extern uint32_t __heap_limit[];
24+
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Base[];
25+
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Length[];
2726

28-
#if !defined(ISR_STACK_SIZE)
29-
#define ISR_STACK_SIZE ((uint32_t)1024)
30-
#endif
27+
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Base[];
28+
extern uint32_t Image$$ARM_LIB_HEAP$$ZI$$Length[];
3129

3230
/*
3331
* mbed entry point for the MICROLIB toolchain
@@ -41,12 +39,11 @@ void _main_init(void) __attribute__((section(".ARM.Collect$$$$000000FF")));
4139
void _main_init(void)
4240
{
4341
/* microlib only supports the two region memory model */
42+
mbed_stack_isr_start = (unsigned char *) Image$$ARM_LIB_STACK$$ZI$$Base;
43+
mbed_stack_isr_size = (uint32_t) Image$$ARM_LIB_STACK$$ZI$$Length;
4444

45-
mbed_heap_start = (unsigned char *)__heap_base;
46-
mbed_heap_size = (uint32_t)__heap_base - (uint32_t)__heap_limit;
47-
48-
mbed_stack_isr_start = (unsigned char *)((uint32_t)__initial_sp - ISR_STACK_SIZE);
49-
mbed_stack_isr_size = ISR_STACK_SIZE;
45+
mbed_heap_start = (unsigned char *) Image$$ARM_LIB_HEAP$$ZI$$Base;
46+
mbed_heap_size = (uint32_t) Image$$ARM_LIB_HEAP$$ZI$$Length;
5047

5148
mbed_init();
5249
mbed_rtos_start();

‎targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct

Lines changed: 45 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,50 @@
1+
#! armcc -E
2+
13
;SAMD21G18A
2-
;256KB FLASH (0x40000) @ 0x000000000
3-
;2KB RAM (0x8000) @ 0x20000000
4+
; 256KB FLASH (0x40000) @ 0x000000000
5+
#if !defined(MBED_APP_START)
6+
#define MBED_APP_START 0x00000000
7+
#endif
8+
9+
; SAMD21G18A: 256KB FLASH (0x40000)
10+
#if !defined(MBED_APP_SIZE)
11+
#define MBED_APP_SIZE 0x40000
12+
#endif
13+
14+
; 32KB RAM (0x8000) @ 0x20000000
15+
#if !defined(MBED_RAM_START)
16+
#define MBED_RAM_START 0x20000000
17+
#endif
18+
19+
#if !defined(MBED_RAM_SIZE)
20+
#define MBED_RAM_SIZE 0x8000
21+
#endif
22+
23+
24+
#if !defined(MBED_BOOT_STACK_SIZE)
25+
#define MBED_BOOT_STACK_SIZE 0x400
26+
#endif
27+
28+
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
29+
#define VECTOR_SIZE 0xB8
30+
31+
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
32+
33+
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
434

35+
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
36+
*.o (RESET, +First)
37+
*(InRoot$$Sections)
38+
.ANY (+RO)
39+
}
540

6-
;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
7-
LR_IROM1 0x00000000 0x40000 { ; load region size_region
8-
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
9-
*.o (RESET, +First)
10-
*(InRoot$$Sections)
11-
.ANY (+RO)
12-
}
41+
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
42+
.ANY (+RW +ZI)
43+
}
1344

14-
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
15-
RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8) { ; RW data
16-
.ANY (+RW +ZI)
17-
}
45+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
46+
}
1847

19-
}
48+
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
49+
}
50+
}

‎targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct

Lines changed: 45 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,50 @@
1+
#! armcc -E
2+
13
;SAMD21J18A
2-
;256KB FLASH (0x40000) @ 0x000000000
3-
;2KB RAM (0x8000) @ 0x20000000
4+
; 256KB FLASH (0x40000) @ 0x000000000
5+
#if !defined(MBED_APP_START)
6+
#define MBED_APP_START 0x00000000
7+
#endif
8+
9+
; SAMD21J18A: 256KB FLASH (0x40000)
10+
#if !defined(MBED_APP_SIZE)
11+
#define MBED_APP_SIZE 0x40000
12+
#endif
13+
14+
; 32KB RAM (0x8000) @ 0x20000000
15+
#if !defined(MBED_RAM_START)
16+
#define MBED_RAM_START 0x20000000
17+
#endif
18+
19+
#if !defined(MBED_RAM_SIZE)
20+
#define MBED_RAM_SIZE 0x8000
21+
#endif
22+
23+
24+
#if !defined(MBED_BOOT_STACK_SIZE)
25+
#define MBED_BOOT_STACK_SIZE 0x400
26+
#endif
27+
28+
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
29+
#define VECTOR_SIZE 0xB8
30+
31+
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
32+
33+
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
434

35+
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
36+
*.o (RESET, +First)
37+
*(InRoot$$Sections)
38+
.ANY (+RO)
39+
}
540

6-
;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
7-
LR_IROM1 0x00000000 0x40000 { ; load region size_region
8-
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
9-
*.o (RESET, +First)
10-
*(InRoot$$Sections)
11-
.ANY (+RO)
12-
}
41+
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
42+
.ANY (+RW +ZI)
43+
}
1344

14-
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
15-
RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8) { ; RW data
16-
.ANY (+RW +ZI)
17-
}
45+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
46+
}
1847

19-
}
48+
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
49+
}
50+
}

‎targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct

Lines changed: 50 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,50 @@
1-
;
2-
SAML21J18A
3-
;
4-
256KB FLASH (0x40000) @ 0x000000000
5-
;
6-
2KB RAM (0x8000) @ 0x20000000
7-
8-
9-
;
10-
SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
11-
LR_IROM1 0x00000000 0x40000 { ;
12-
load region size_region
13-
ER_IROM1 0x00000000 0x40000 { ;
14-
load address = execution address
15-
*.o (RESET, +First)
16-
*(InRoot$$Sections)
17-
.ANY (+RO)
18-
}
19-
20-
;
21-
[RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
22-
RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8)
23-
{
24-
;
25-
RW data
26-
.ANY (+RW +ZI)
27-
}
28-
29-
}
1+
#! armcc -E
2+
3+
;SAMD21J18A
4+
; 256KB FLASH (0x40000) @ 0x000000000
5+
#if !defined(MBED_APP_START)
6+
#define MBED_APP_START 0x00000000
7+
#endif
8+
9+
; SAMD21J18A: 256KB FLASH (0x40000)
10+
#if !defined(MBED_APP_SIZE)
11+
#define MBED_APP_SIZE 0x40000
12+
#endif
13+
14+
; 32KB RAM (0x8000) @ 0x20000000
15+
#if !defined(MBED_RAM_START)
16+
#define MBED_RAM_START 0x20000000
17+
#endif
18+
19+
#if !defined(MBED_RAM_SIZE)
20+
#define MBED_RAM_SIZE 0x8000
21+
#endif
22+
23+
24+
#if !defined(MBED_BOOT_STACK_SIZE)
25+
#define MBED_BOOT_STACK_SIZE 0x400
26+
#endif
27+
28+
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
29+
#define VECTOR_SIZE 0xB8
30+
31+
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
32+
33+
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
34+
35+
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
36+
*.o (RESET, +First)
37+
*(InRoot$$Sections)
38+
.ANY (+RO)
39+
}
40+
41+
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
42+
.ANY (+RW +ZI)
43+
}
44+
45+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
46+
}
47+
48+
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
49+
}
50+
}

‎targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct

Lines changed: 45 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,50 @@
1+
#! armcc -E
2+
13
;SAMR21G18A
2-
;256KB FLASH (0x40000) @ 0x000000000
3-
;2KB RAM (0x8000) @ 0x20000000
4+
; 256KB FLASH (0x40000) @ 0x000000000
5+
#if !defined(MBED_APP_START)
6+
#define MBED_APP_START 0x00000000
7+
#endif
8+
9+
; SAMR21G18A: 256KB FLASH (0x40000)
10+
#if !defined(MBED_APP_SIZE)
11+
#define MBED_APP_SIZE 0x40000
12+
#endif
13+
14+
; 32KB RAM (0x8000) @ 0x20000000
15+
#if !defined(MBED_RAM_START)
16+
#define MBED_RAM_START 0x20000000
17+
#endif
18+
19+
#if !defined(MBED_RAM_SIZE)
20+
#define MBED_RAM_SIZE 0x8000
21+
#endif
22+
23+
24+
#if !defined(MBED_BOOT_STACK_SIZE)
25+
#define MBED_BOOT_STACK_SIZE 0x400
26+
#endif
27+
28+
; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
29+
#define VECTOR_SIZE 0xB0
30+
31+
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
32+
33+
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
434

35+
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
36+
*.o (RESET, +First)
37+
*(InRoot$$Sections)
38+
.ANY (+RO)
39+
}
540

6-
;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
7-
LR_IROM1 0x00000000 0x40000 { ; load region size_region
8-
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
9-
*.o (RESET, +First)
10-
*(InRoot$$Sections)
11-
.ANY (+RO)
12-
}
41+
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
42+
.ANY (+RW +ZI)
43+
}
1344

14-
; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
15-
RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0) { ; RW data
16-
.ANY (+RW +ZI)
17-
}
45+
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
46+
}
1847

19-
}
48+
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
49+
}
50+
}

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