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Merge pull request #11542 from morser499/pr/target-update
Update Cypress targets
2 parents 5108f91 + f0fdee4 commit f987fe0

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‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,14 @@
2424

2525
#include "cycfg_clocks.h"
2626

27+
#if defined (CY_USING_HAL)
28+
const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj =
29+
{
30+
.type = CYHAL_RSC_CLOCK,
31+
.block_num = CYBSP_UART_CLK_DIV_HW,
32+
.channel_num = CYBSP_UART_CLK_DIV_NUM,
33+
};
34+
#endif //defined (CY_USING_HAL)
2735
#if defined (CY_USING_HAL)
2836
const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj =
2937
{
@@ -52,6 +60,13 @@
5260

5361
void init_cycfg_clocks(void)
5462
{
63+
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
64+
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0U, 719U);
65+
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0U);
66+
#if defined (CY_USING_HAL)
67+
cyhal_hwmgr_reserve(&CYBSP_UART_CLK_DIV_obj);
68+
#endif //defined (CY_USING_HAL)
69+
5570
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_16_BIT, 1U);
5671
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 1U, 77U);
5772
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 1U);

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,9 @@
3535
extern "C" {
3636
#endif
3737

38+
#define CYBSP_UART_CLK_DIV_ENABLED 1U
39+
#define CYBSP_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
40+
#define CYBSP_UART_CLK_DIV_NUM 0U
3841
#define CYBSP_BT_UART_CLK_DIV_ENABLED 1U
3942
#define CYBSP_BT_UART_CLK_DIV_HW CY_SYSCLK_DIV_16_BIT
4043
#define CYBSP_BT_UART_CLK_DIV_NUM 1U
@@ -45,6 +48,9 @@ extern "C" {
4548
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
4649
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
4750

51+
#if defined (CY_USING_HAL)
52+
extern const cyhal_resource_inst_t CYBSP_UART_CLK_DIV_obj;
53+
#endif //defined (CY_USING_HAL)
4854
#if defined (CY_USING_HAL)
4955
extern const cyhal_resource_inst_t CYBSP_BT_UART_CLK_DIV_obj;
5056
#endif //defined (CY_USING_HAL)

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

Lines changed: 44 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,20 @@
2424

2525
#include "cycfg_peripherals.h"
2626

27+
#define CYBSP_USBUART_INTR_LVL_SEL (CY_USBFS_DEV_DRV_SET_SOF_LVL(0x1U) | \
28+
CY_USBFS_DEV_DRV_SET_BUS_RESET_LVL(0x2U) | \
29+
CY_USBFS_DEV_DRV_SET_EP0_LVL(0x2U) | \
30+
CY_USBFS_DEV_DRV_SET_LPM_LVL(0x0U) | \
31+
CY_USBFS_DEV_DRV_SET_ARB_EP_LVL(0x0U) | \
32+
CY_USBFS_DEV_DRV_SET_EP1_LVL(0x1U) | \
33+
CY_USBFS_DEV_DRV_SET_EP2_LVL(0x1U) | \
34+
CY_USBFS_DEV_DRV_SET_EP3_LVL(0x1U) | \
35+
CY_USBFS_DEV_DRV_SET_EP4_LVL(0x1U) | \
36+
CY_USBFS_DEV_DRV_SET_EP5_LVL(0x1U) | \
37+
CY_USBFS_DEV_DRV_SET_EP6_LVL(0x1U) | \
38+
CY_USBFS_DEV_DRV_SET_EP7_LVL(0x1U) | \
39+
CY_USBFS_DEV_DRV_SET_EP8_LVL(0x1U))
40+
2741
cy_stc_csd_context_t cy_csd_0_context =
2842
{
2943
.lockKey = CY_CSD_NONE_KEY,
@@ -136,6 +150,31 @@ const cy_stc_rtc_config_t CYBSP_RTC_config =
136150
.channel_num = 0U,
137151
};
138152
#endif //defined (CY_USING_HAL)
153+
const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config =
154+
{
155+
.mode = CY_USBFS_DEV_DRV_EP_MANAGEMENT_CPU,
156+
.epAccess = CY_USBFS_DEV_DRV_USE_8_BITS_DR,
157+
.epBuffer = NULL,
158+
.epBufferSize = 0U,
159+
.dmaConfig[0] = NULL,
160+
.dmaConfig[1] = NULL,
161+
.dmaConfig[2] = NULL,
162+
.dmaConfig[3] = NULL,
163+
.dmaConfig[4] = NULL,
164+
.dmaConfig[5] = NULL,
165+
.dmaConfig[6] = NULL,
166+
.dmaConfig[7] = NULL,
167+
.enableLpm = false,
168+
.intrLevelSel = CYBSP_USBUART_INTR_LVL_SEL,
169+
};
170+
#if defined (CY_USING_HAL)
171+
const cyhal_resource_inst_t CYBSP_USBUART_obj =
172+
{
173+
.type = CYHAL_RSC_USB,
174+
.block_num = 0U,
175+
.channel_num = 0U,
176+
};
177+
#endif //defined (CY_USING_HAL)
139178

140179

141180
void init_cycfg_peripherals(void)
@@ -163,4 +202,9 @@ void init_cycfg_peripherals(void)
163202
#if defined (CY_USING_HAL)
164203
cyhal_hwmgr_reserve(&CYBSP_RTC_obj);
165204
#endif //defined (CY_USING_HAL)
205+
206+
Cy_SysClk_PeriphAssignDivider(PCLK_USB_CLOCK_DEV_BRS, CY_SYSCLK_DIV_16_BIT, 0U);
207+
#if defined (CY_USING_HAL)
208+
cyhal_hwmgr_reserve(&CYBSP_USBUART_obj);
209+
#endif //defined (CY_USING_HAL)
166210
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737
#include "cycfg_qspi_memslot.h"
3838
#include "cy_mcwdt.h"
3939
#include "cy_rtc.h"
40+
#include "cy_usbfs_dev_drv.h"
4041

4142
#if defined(__cplusplus)
4243
extern "C" {
@@ -113,6 +114,14 @@ extern "C" {
113114
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
114115
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
115116
#define CYBSP_RTC_YEAR_OFFSET (0U)
117+
#define CYBSP_USBUART_ENABLED 1U
118+
#define CYBSP_USBUART_ACTIVE_ENDPOINTS_MASK 0U
119+
#define CYBSP_USBUART_ENDPOINTS_BUFFER_SIZE 512U
120+
#define CYBSP_USBUART_ENDPOINTS_ACCESS_TYPE 0U
121+
#define CYBSP_USBUART_HW USBFS0
122+
#define CYBSP_USBUART_HI_IRQ usb_interrupt_hi_IRQn
123+
#define CYBSP_USBUART_MED_IRQ usb_interrupt_med_IRQn
124+
#define CYBSP_USBUART_LO_IRQ usb_interrupt_lo_IRQn
116125

117126
extern cy_stc_csd_context_t cy_csd_0_context;
118127
extern const cy_stc_scb_uart_config_t CYBSP_BT_UART_config;
@@ -135,6 +144,10 @@ extern const cy_stc_rtc_config_t CYBSP_RTC_config;
135144
#if defined (CY_USING_HAL)
136145
extern const cyhal_resource_inst_t CYBSP_RTC_obj;
137146
#endif //defined (CY_USING_HAL)
147+
extern const cy_stc_usbfs_dev_drv_config_t CYBSP_USBUART_config;
148+
#if defined (CY_USING_HAL)
149+
extern const cyhal_resource_inst_t CYBSP_USBUART_obj;
150+
#endif //defined (CY_USING_HAL)
138151

139152
void init_cycfg_peripherals(void);
140153

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

Lines changed: 87 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,54 @@ const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config =
216216
.channel_num = CYBSP_QSPI_SPI_CLOCK_PIN,
217217
};
218218
#endif //defined (CY_USING_HAL)
219+
const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config =
220+
{
221+
.outVal = 1,
222+
.driveMode = CY_GPIO_DM_ANALOG,
223+
.hsiom = CYBSP_USB_DP_HSIOM,
224+
.intEdge = CY_GPIO_INTR_DISABLE,
225+
.intMask = 0UL,
226+
.vtrip = CY_GPIO_VTRIP_CMOS,
227+
.slewRate = CY_GPIO_SLEW_FAST,
228+
.driveSel = CY_GPIO_DRIVE_1_2,
229+
.vregEn = 0UL,
230+
.ibufMode = 0UL,
231+
.vtripSel = 0UL,
232+
.vrefSel = 0UL,
233+
.vohSel = 0UL,
234+
};
235+
#if defined (CY_USING_HAL)
236+
const cyhal_resource_inst_t CYBSP_USB_DP_obj =
237+
{
238+
.type = CYHAL_RSC_GPIO,
239+
.block_num = CYBSP_USB_DP_PORT_NUM,
240+
.channel_num = CYBSP_USB_DP_PIN,
241+
};
242+
#endif //defined (CY_USING_HAL)
243+
const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config =
244+
{
245+
.outVal = 1,
246+
.driveMode = CY_GPIO_DM_ANALOG,
247+
.hsiom = CYBSP_USB_DM_HSIOM,
248+
.intEdge = CY_GPIO_INTR_DISABLE,
249+
.intMask = 0UL,
250+
.vtrip = CY_GPIO_VTRIP_CMOS,
251+
.slewRate = CY_GPIO_SLEW_FAST,
252+
.driveSel = CY_GPIO_DRIVE_1_2,
253+
.vregEn = 0UL,
254+
.ibufMode = 0UL,
255+
.vtripSel = 0UL,
256+
.vrefSel = 0UL,
257+
.vohSel = 0UL,
258+
};
259+
#if defined (CY_USING_HAL)
260+
const cyhal_resource_inst_t CYBSP_USB_DM_obj =
261+
{
262+
.type = CYHAL_RSC_GPIO,
263+
.block_num = CYBSP_USB_DM_PORT_NUM,
264+
.channel_num = CYBSP_USB_DM_PIN,
265+
};
266+
#endif //defined (CY_USING_HAL)
219267
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
220268
{
221269
.outVal = 1,
@@ -408,6 +456,30 @@ const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config =
408456
.channel_num = CYBSP_BT_HOST_WAKE_PIN,
409457
};
410458
#endif //defined (CY_USING_HAL)
459+
const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config =
460+
{
461+
.outVal = 1,
462+
.driveMode = CY_GPIO_DM_ANALOG,
463+
.hsiom = CYBSP_WIFI_HOST_WAKE_HSIOM,
464+
.intEdge = CY_GPIO_INTR_RISING,
465+
.intMask = 1UL,
466+
.vtrip = CY_GPIO_VTRIP_CMOS,
467+
.slewRate = CY_GPIO_SLEW_FAST,
468+
.driveSel = CY_GPIO_DRIVE_1_2,
469+
.vregEn = 0UL,
470+
.ibufMode = 0UL,
471+
.vtripSel = 0UL,
472+
.vrefSel = 0UL,
473+
.vohSel = 0UL,
474+
};
475+
#if defined (CY_USING_HAL)
476+
const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj =
477+
{
478+
.type = CYHAL_RSC_GPIO,
479+
.block_num = CYBSP_WIFI_HOST_WAKE_PORT_NUM,
480+
.channel_num = CYBSP_WIFI_HOST_WAKE_PIN,
481+
};
482+
#endif //defined (CY_USING_HAL)
411483
const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config =
412484
{
413485
.outVal = 1,
@@ -812,6 +884,16 @@ void init_cycfg_pins(void)
812884
cyhal_hwmgr_reserve(&CYBSP_QSPI_SPI_CLOCK_obj);
813885
#endif //defined (CY_USING_HAL)
814886

887+
Cy_GPIO_Pin_Init(CYBSP_USB_DP_PORT, CYBSP_USB_DP_PIN, &CYBSP_USB_DP_config);
888+
#if defined (CY_USING_HAL)
889+
cyhal_hwmgr_reserve(&CYBSP_USB_DP_obj);
890+
#endif //defined (CY_USING_HAL)
891+
892+
Cy_GPIO_Pin_Init(CYBSP_USB_DM_PORT, CYBSP_USB_DM_PIN, &CYBSP_USB_DM_config);
893+
#if defined (CY_USING_HAL)
894+
cyhal_hwmgr_reserve(&CYBSP_USB_DM_obj);
895+
#endif //defined (CY_USING_HAL)
896+
815897
#if defined (CY_USING_HAL)
816898
cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
817899
#endif //defined (CY_USING_HAL)
@@ -851,6 +933,11 @@ void init_cycfg_pins(void)
851933
cyhal_hwmgr_reserve(&CYBSP_BT_HOST_WAKE_obj);
852934
#endif //defined (CY_USING_HAL)
853935

936+
Cy_GPIO_Pin_Init(CYBSP_WIFI_HOST_WAKE_PORT, CYBSP_WIFI_HOST_WAKE_PIN, &CYBSP_WIFI_HOST_WAKE_config);
937+
#if defined (CY_USING_HAL)
938+
cyhal_hwmgr_reserve(&CYBSP_WIFI_HOST_WAKE_obj);
939+
#endif //defined (CY_USING_HAL)
940+
854941
Cy_GPIO_Pin_Init(CYBSP_EZI2C_SCL_PORT, CYBSP_EZI2C_SCL_PIN, &CYBSP_EZI2C_SCL_config);
855942
#if defined (CY_USING_HAL)
856943
cyhal_hwmgr_reserve(&CYBSP_EZI2C_SCL_obj);

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

Lines changed: 84 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -228,6 +228,54 @@ extern "C" {
228228
#if defined (CY_USING_HAL)
229229
#define CYBSP_QSPI_SPI_CLOCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG
230230
#endif //defined (CY_USING_HAL)
231+
#define CYBSP_USB_DP_ENABLED 1U
232+
#define CYBSP_USB_DP_PORT GPIO_PRT14
233+
#define CYBSP_USB_DP_PORT_NUM 14U
234+
#define CYBSP_USB_DP_PIN 0U
235+
#define CYBSP_USB_DP_NUM 0U
236+
#define CYBSP_USB_DP_DRIVEMODE CY_GPIO_DM_ANALOG
237+
#define CYBSP_USB_DP_INIT_DRIVESTATE 1
238+
#ifndef ioss_0_port_14_pin_0_HSIOM
239+
#define ioss_0_port_14_pin_0_HSIOM HSIOM_SEL_GPIO
240+
#endif
241+
#define CYBSP_USB_DP_HSIOM ioss_0_port_14_pin_0_HSIOM
242+
#define CYBSP_USB_DP_IRQ ioss_interrupts_gpio_14_IRQn
243+
#if defined (CY_USING_HAL)
244+
#define CYBSP_USB_DP_HAL_PORT_PIN P14_0
245+
#endif //defined (CY_USING_HAL)
246+
#if defined (CY_USING_HAL)
247+
#define CYBSP_USB_DP_HAL_IRQ CYHAL_GPIO_IRQ_NONE
248+
#endif //defined (CY_USING_HAL)
249+
#if defined (CY_USING_HAL)
250+
#define CYBSP_USB_DP_HAL_DIR CYHAL_GPIO_DIR_INPUT
251+
#endif //defined (CY_USING_HAL)
252+
#if defined (CY_USING_HAL)
253+
#define CYBSP_USB_DP_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
254+
#endif //defined (CY_USING_HAL)
255+
#define CYBSP_USB_DM_ENABLED 1U
256+
#define CYBSP_USB_DM_PORT GPIO_PRT14
257+
#define CYBSP_USB_DM_PORT_NUM 14U
258+
#define CYBSP_USB_DM_PIN 1U
259+
#define CYBSP_USB_DM_NUM 1U
260+
#define CYBSP_USB_DM_DRIVEMODE CY_GPIO_DM_ANALOG
261+
#define CYBSP_USB_DM_INIT_DRIVESTATE 1
262+
#ifndef ioss_0_port_14_pin_1_HSIOM
263+
#define ioss_0_port_14_pin_1_HSIOM HSIOM_SEL_GPIO
264+
#endif
265+
#define CYBSP_USB_DM_HSIOM ioss_0_port_14_pin_1_HSIOM
266+
#define CYBSP_USB_DM_IRQ ioss_interrupts_gpio_14_IRQn
267+
#if defined (CY_USING_HAL)
268+
#define CYBSP_USB_DM_HAL_PORT_PIN P14_1
269+
#endif //defined (CY_USING_HAL)
270+
#if defined (CY_USING_HAL)
271+
#define CYBSP_USB_DM_HAL_IRQ CYHAL_GPIO_IRQ_NONE
272+
#endif //defined (CY_USING_HAL)
273+
#if defined (CY_USING_HAL)
274+
#define CYBSP_USB_DM_HAL_DIR CYHAL_GPIO_DIR_INPUT
275+
#endif //defined (CY_USING_HAL)
276+
#if defined (CY_USING_HAL)
277+
#define CYBSP_USB_DM_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
278+
#endif //defined (CY_USING_HAL)
231279
#define CYBSP_CSD_RX_ENABLED 1U
232280
#define CYBSP_CSD_RX_PORT GPIO_PRT1
233281
#define CYBSP_CSD_RX_PORT_NUM 1U
@@ -420,6 +468,30 @@ extern "C" {
420468
#if defined (CY_USING_HAL)
421469
#define CYBSP_BT_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
422470
#endif //defined (CY_USING_HAL)
471+
#define CYBSP_WIFI_HOST_WAKE_ENABLED 1U
472+
#define CYBSP_WIFI_HOST_WAKE_PORT GPIO_PRT4
473+
#define CYBSP_WIFI_HOST_WAKE_PORT_NUM 4U
474+
#define CYBSP_WIFI_HOST_WAKE_PIN 1U
475+
#define CYBSP_WIFI_HOST_WAKE_NUM 1U
476+
#define CYBSP_WIFI_HOST_WAKE_DRIVEMODE CY_GPIO_DM_ANALOG
477+
#define CYBSP_WIFI_HOST_WAKE_INIT_DRIVESTATE 1
478+
#ifndef ioss_0_port_4_pin_1_HSIOM
479+
#define ioss_0_port_4_pin_1_HSIOM HSIOM_SEL_GPIO
480+
#endif
481+
#define CYBSP_WIFI_HOST_WAKE_HSIOM ioss_0_port_4_pin_1_HSIOM
482+
#define CYBSP_WIFI_HOST_WAKE_IRQ ioss_interrupts_gpio_4_IRQn
483+
#if defined (CY_USING_HAL)
484+
#define CYBSP_WIFI_HOST_WAKE_HAL_PORT_PIN P4_1
485+
#endif //defined (CY_USING_HAL)
486+
#if defined (CY_USING_HAL)
487+
#define CYBSP_WIFI_HOST_WAKE_HAL_IRQ CYHAL_GPIO_IRQ_RISE
488+
#endif //defined (CY_USING_HAL)
489+
#if defined (CY_USING_HAL)
490+
#define CYBSP_WIFI_HOST_WAKE_HAL_DIR CYHAL_GPIO_DIR_INPUT
491+
#endif //defined (CY_USING_HAL)
492+
#if defined (CY_USING_HAL)
493+
#define CYBSP_WIFI_HOST_WAKE_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
494+
#endif //defined (CY_USING_HAL)
423495
#define CYBSP_EZI2C_SCL_ENABLED 1U
424496
#define CYBSP_EZI2C_SCL_PORT GPIO_PRT6
425497
#define CYBSP_EZI2C_SCL_PORT_NUM 6U
@@ -813,6 +885,14 @@ extern const cy_stc_gpio_pin_config_t CYBSP_QSPI_SPI_CLOCK_config;
813885
#if defined (CY_USING_HAL)
814886
extern const cyhal_resource_inst_t CYBSP_QSPI_SPI_CLOCK_obj;
815887
#endif //defined (CY_USING_HAL)
888+
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DP_config;
889+
#if defined (CY_USING_HAL)
890+
extern const cyhal_resource_inst_t CYBSP_USB_DP_obj;
891+
#endif //defined (CY_USING_HAL)
892+
extern const cy_stc_gpio_pin_config_t CYBSP_USB_DM_config;
893+
#if defined (CY_USING_HAL)
894+
extern const cyhal_resource_inst_t CYBSP_USB_DM_obj;
895+
#endif //defined (CY_USING_HAL)
816896
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config;
817897
#if defined (CY_USING_HAL)
818898
extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj;
@@ -845,6 +925,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_BT_HOST_WAKE_config;
845925
#if defined (CY_USING_HAL)
846926
extern const cyhal_resource_inst_t CYBSP_BT_HOST_WAKE_obj;
847927
#endif //defined (CY_USING_HAL)
928+
extern const cy_stc_gpio_pin_config_t CYBSP_WIFI_HOST_WAKE_config;
929+
#if defined (CY_USING_HAL)
930+
extern const cyhal_resource_inst_t CYBSP_WIFI_HOST_WAKE_obj;
931+
#endif //defined (CY_USING_HAL)
848932
extern const cy_stc_gpio_pin_config_t CYBSP_EZI2C_SCL_config;
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#if defined (CY_USING_HAL)
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extern const cyhal_resource_inst_t CYBSP_EZI2C_SCL_obj;

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