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Merge pull request #11444 from jeromecoutant/PR_QSPI_EXTERNAL
QSPI : Define default pins at drivers level
2 parents 9534327 + 23e6840 commit fe12608

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5 files changed

+58
-47
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5 files changed

+58
-47
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‎TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -17,23 +17,8 @@
1717
#ifndef MBED_FLASH_CONFIGS_H
1818
#define MBED_FLASH_CONFIGS_H
1919

20-
#if defined(TARGET_DISCO_L475VG_IOT01A)
21-
#include "MX25RXX35F_config.h" // MX25R6435F
22-
23-
#elif defined(TARGET_DISCO_F413ZH)
24-
#include "N25Q128A_config.h" // N25Q128A13EF840F
25-
26-
#elif defined(TARGET_DISCO_F746NG)
27-
#include "N25Q128A_config.h" // N25Q128A13EF840E
28-
29-
#elif defined(TARGET_DISCO_F469NI)
30-
#include "N25Q128A_config.h" // N25Q128A13EF840E
31-
32-
#elif defined(TARGET_DISCO_F769NI)
33-
#include "MX25L51245G_config.h" // MX25L51245G
34-
35-
#elif defined(TARGET_DISCO_L4R9I)
36-
#include "MX25LM51245G_config.h" // MX25LM51245G
20+
#if defined(TARGET_MX25R6435F)
21+
#include "MX25RXX35F_config.h"
3722

3823
#elif defined(TARGET_DISCO_L476VG)
3924
#include "N25Q128A_config.h" // N25Q128A13EF840E
@@ -43,6 +28,15 @@
4328
#undef QSPI_CMD_WRITE_DPI
4429
#undef QSPI_CMD_WRITE_QPI
4530

31+
#elif defined(TARGET_N25Q128A)
32+
#include "N25Q128A_config.h"
33+
34+
#elif defined(TARGET_MX25L51245G)
35+
#include "MX25L51245G_config.h"
36+
37+
#elif defined(TARGET_MX25LM51245G)
38+
#include "MX25LM51245G_config.h"
39+
4640
#elif defined(TARGET_RHOMBIO_L476DMW1K)
4741
#include "MT25Q_config.h" // MT25QL128ABA1EW7
4842
/* See STM32L476 Errata Sheet, it is not possible to use Dual-/Quad-mode for the command phase */
@@ -51,9 +45,6 @@
5145
#undef QSPI_CMD_WRITE_DPI
5246
#undef QSPI_CMD_WRITE_QPI
5347

54-
#elif defined(TARGET_DISCO_L496AG)
55-
#include "MX25RXX35F_config.h" // MX25R6435F
56-
5748
#elif defined(TARGET_NRF52840)
5849
#include "NORDIC/NRF52840_DK/flash_config.h"
5950

@@ -88,5 +79,6 @@
8879
#include "S25FL128S_config.h"
8980

9081
#endif
82+
9183
#endif // MBED_FLASH_CONFIGS_H
9284

‎TESTS/mbed_hal/qspi/main.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -70,12 +70,12 @@ uint8_t rx_buf[DATA_SIZE_1024];
7070

7171

7272
// some target defines QSPI pins as integers thus conversion needed
73-
#define QPIN_0 static_cast<PinName>(QSPI_FLASH1_IO0)
74-
#define QPIN_1 static_cast<PinName>(QSPI_FLASH1_IO1)
75-
#define QPIN_2 static_cast<PinName>(QSPI_FLASH1_IO2)
76-
#define QPIN_3 static_cast<PinName>(QSPI_FLASH1_IO3)
77-
#define QSCK static_cast<PinName>(QSPI_FLASH1_SCK)
78-
#define QCSN static_cast<PinName>(QSPI_FLASH1_CSN)
73+
#define QPIN_0 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO0)
74+
#define QPIN_1 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO1)
75+
#define QPIN_2 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO2)
76+
#define QPIN_3 static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_IO3)
77+
#define QSCK static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_SCK)
78+
#define QCSN static_cast<PinName>(MBED_CONF_DRIVERS_QSPI_CSN)
7979

8080

8181
static uint32_t gen_flash_address()

‎components/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json

Lines changed: 9 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,39 +1,27 @@
11
{
22
"name": "qspif",
33
"config": {
4-
"QSPI_IO0": "QSPI_FLASH1_IO0",
5-
"QSPI_IO1": "QSPI_FLASH1_IO1",
6-
"QSPI_IO2": "QSPI_FLASH1_IO2",
7-
"QSPI_IO3": "QSPI_FLASH1_IO3",
8-
"QSPI_SCK": "QSPI_FLASH1_SCK",
9-
"QSPI_CSN": "QSPI_FLASH1_CSN",
4+
"QSPI_IO0": "MBED_CONF_DRIVERS_QSPI_IO0",
5+
"QSPI_IO1": "MBED_CONF_DRIVERS_QSPI_IO1",
6+
"QSPI_IO2": "MBED_CONF_DRIVERS_QSPI_IO2",
7+
"QSPI_IO3": "MBED_CONF_DRIVERS_QSPI_IO3",
8+
"QSPI_SCK": "MBED_CONF_DRIVERS_QSPI_SCK",
9+
"QSPI_CSN": "MBED_CONF_DRIVERS_QSPI_CSN",
1010
"QSPI_POLARITY_MODE": 0,
1111
"QSPI_FREQ": "40000000",
1212
"QSPI_MIN_READ_SIZE": "1",
1313
"QSPI_MIN_PROG_SIZE": "1"
1414
},
1515
"target_overrides": {
16-
"DISCO_F413ZH": {
17-
"QSPI_FREQ": "80000000"
18-
},
19-
"DISCO_L475VG_IOT01A": {
16+
"MX25R6435F": {
2017
"QSPI_FREQ": "8000000"
2118
},
22-
"DISCO_L476VG": {
23-
"QSPI_FREQ": "80000000"
24-
},
25-
"DISCO_L496AG": {
19+
"MX25L51245G": {
2620
"QSPI_FREQ": "8000000"
2721
},
28-
"DISCO_F469NI": {
22+
"N25Q128A": {
2923
"QSPI_FREQ": "80000000"
3024
},
31-
"DISCO_F746NG": {
32-
"QSPI_FREQ": "80000000"
33-
},
34-
"DISCO_F769NI": {
35-
"QSPI_FREQ": "8000000"
36-
},
3725
"MCU_NRF52840": {
3826
"QSPI_FREQ": "32000000",
3927
"QSPI_MIN_READ_SIZE": "4",

‎drivers/mbed_lib.json

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,30 @@
1212
"spi_count_max": {
1313
"help": "The maximum number of SPI peripherals used at the same time. Determines RAM allocated for SPI peripheral management. If null, limit determined by hardware.",
1414
"value": null
15+
},
16+
"qspi_io0": {
17+
"help": "QSPI data I/O 0 pin",
18+
"value": "QSPI_FLASH1_IO0"
19+
},
20+
"qspi_io1": {
21+
"help": "QSPI data I/O 1 pin",
22+
"value": "QSPI_FLASH1_IO1"
23+
},
24+
"qspi_io2": {
25+
"help": "QSPI data I/O 2 pin",
26+
"value": "QSPI_FLASH1_IO2"
27+
},
28+
"qspi_io3": {
29+
"help": "QSPI data I/O 3 pin",
30+
"value": "QSPI_FLASH1_IO3"
31+
},
32+
"qspi_sck": {
33+
"help": "QSPI clock pin",
34+
"value": "QSPI_FLASH1_SCK"
35+
},
36+
"qspi_csn": {
37+
"help": "QSPI chip select pin",
38+
"value": "QSPI_FLASH1_CSN"
1539
}
1640
}
1741
}

‎targets/targets.json

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2745,6 +2745,7 @@
27452745
"supported_form_factors": ["ARDUINO"],
27462746
"core": "Cortex-M4F",
27472747
"extra_labels_add": [
2748+
"N25Q128A",
27482749
"STM32F4",
27492750
"STM32F413xx",
27502751
"STM32F413ZH",
@@ -4139,6 +4140,7 @@
41394140
"supported_form_factors": ["ARDUINO"],
41404141
"core": "Cortex-M4F",
41414142
"extra_labels_add": [
4143+
"N25Q128A",
41424144
"STM32F4",
41434145
"STM32F469",
41444146
"STM32F469NI",
@@ -4300,6 +4302,7 @@
43004302
"inherits": ["FAMILY_STM32"],
43014303
"core": "Cortex-M7F",
43024304
"extra_labels_add": [
4305+
"N25Q128A",
43034306
"STM32F7",
43044307
"STM32F746",
43054308
"STM32F746xG",
@@ -4354,6 +4357,7 @@
43544357
"inherits": ["FAMILY_STM32"],
43554358
"core": "Cortex-M7FD",
43564359
"extra_labels_add": [
4360+
"MX25L51245G",
43574361
"STM32F7",
43584362
"STM32F769",
43594363
"STM32F769xI",
@@ -4412,6 +4416,7 @@
44124416
"inherits": ["FAMILY_STM32"],
44134417
"core": "Cortex-M4F",
44144418
"extra_labels_add": [
4419+
"MX25R6435F",
44154420
"STM32L4",
44164421
"STM32L475xG",
44174422
"STM32L475VG"
@@ -4485,6 +4490,7 @@
44854490
"inherits": ["FAMILY_STM32"],
44864491
"core": "Cortex-M4F",
44874492
"extra_labels_add": [
4493+
"N25Q128A",
44884494
"STM32L4",
44894495
"STM32L476xG",
44904496
"STM32L476VG"
@@ -8314,6 +8320,7 @@
83148320
"supported_form_factors": ["ARDUINO", "STMOD", "PMOD"],
83158321
"core": "Cortex-M4F",
83168322
"extra_labels_add": [
8323+
"MX25R6435F",
83178324
"STM32L4",
83188325
"STM32L496AG",
83198326
"STM32L496xG"

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