Merge pull request #2866 from pradeep-gr/master

MBED OS 3 to 5 changes added for SPI

Author: sg-

targets/TARGET_ONSEMI/TARGET_NCS36510/Pad.c

@@ -108,18 +108,18 @@ boolean fPadIOCtrl(uint8_t PadNum, uint8_t OutputDriveStrength, uint8_t OutputDr
 {
     PadReg_t *PadRegOffset;
     /** \verbatim
-    	Table: O/p drive strength
-
-    		Drive strength	3.3V (min/typ/max)	1V (min/typ/max)
-    		000  	 		1/1.4/2.1 mA		0.043/0.07/0.11 mA
-    		001  	 		2/2.7/4.1 mA		0.086/0.15/0.215 mA
-    		010  	 		4.1/5.3/7.8 mA		0.188/0.3/0.4 mA
-    		011  	 		8.1/10.4/15 8 mA	0.4/0.6/0.81 mA
-    		100  	 		20.8/26/37 mA*		1/1.6/2.2 mA
-    		101  	 		40.5/50/70 mA*	    2/3/4.3 mA
-    		11x  	 		57/73/102 mA*   	3/4.6/6.2 mA
-
-    	*Values are only accessible when CDBGPWRUPREQ is high.  This limits the maximum output current in functional mode. \endverbatim */
+        Table: O/p drive strength
+
+            Drive strength    3.3V (min/typ/max)    1V (min/typ/max)
+            000               1/1.4/2.1 mA        0.043/0.07/0.11 mA
+            001               2/2.7/4.1 mA        0.086/0.15/0.215 mA
+            010               4.1/5.3/7.8 mA        0.188/0.3/0.4 mA
+            011               8.1/10.4/15 8 mA    0.4/0.6/0.81 mA
+            100               20.8/26/37 mA*        1/1.6/2.2 mA
+            101               40.5/50/70 mA*        2/3/4.3 mA
+            11x               57/73/102 mA*       3/4.6/6.2 mA
+
+        *Values are only accessible when CDBGPWRUPREQ is high.  This limits the maximum output current in functional mode. \endverbatim */
 
 
     if((PadNum  <= PAD_NUM_OF_IO) &&

targets/TARGET_ONSEMI/TARGET_NCS36510/PeripheralPins.c

@@ -67,31 +67,39 @@ const PinMap PinMap_SPI_SCLK[] = {
     {SPI1_SCLK_2, SPI_0, 6},
     {SPI1_SCLK_3, SPI_0, 6},
     {SPI2_SCLK,   SPI_1, 6},
-    {NC, 		  NC,    0}
+    {NC,          NC,    0}
 };
 
 const PinMap PinMap_SPI_MOSI[] = {
     /*todo: other pins are possible, need to add */
     {SPI1_SDATAO_2, SPI_0, 6},
     {SPI1_SDATAO_3, SPI_0, 6},
-    {SPI2_SDATAO, 	SPI_1, 6},
-    {NC, 			NC,    0}
+    {SPI2_SDATAO,   SPI_1, 6},
+    {NC,            NC,    0}
 };
 
 const PinMap PinMap_SPI_MISO[] = {
     /*todo: other pins are possible, need to add */
     {SPI1_SDATAI_2, SPI_0, 6},
     {SPI1_SDATAI_3, SPI_0, 6},
-    {SPI2_SDATAI, 	SPI_1, 6},
-    {NC, 			NC,    0}
+    {SPI2_SDATAI,   SPI_1, 6},
+    {NC,            NC,    0}
 };
 
 const PinMap PinMap_SPI_SSEL[] = {
     /*todo: other pins are possible, need to add */
     /* TODO what about SSNO */
-    {SPI1_SSNI_2, SPI_0, 6},
-    {SPI2_SSNI,   SPI_1, 6},
-    {NC, 		  NC,    0}
+    {SPI1_SSNO0_1, SPI_0, 6},
+    {SPI1_SSNO1_1, SPI_0, 6},
+    {SPI1_SSNO2_1, SPI_0, 6},
+    {SPI1_SSNO3_1, SPI_0, 6},
+    {SPI1_SSNI_2,  SPI_0, 6},
+    {SPI1_SSNO0_2, SPI_0, 6},
+    {SPI1_SSNO1_2, SPI_0, 6},
+    {SPI1_SSNO2_2, SPI_0, 6},
+    {SPI2_SSNI,    SPI_1, 6},
+    {SPI2_SSNO0,   SPI_1, 6},
+    {NC,           NC,    0}
 };
 
 

targets/TARGET_ONSEMI/TARGET_NCS36510/PinNames.h

@@ -37,7 +37,7 @@ extern "C" {
 #endif
 
 typedef enum {
-    GPIO0	= 0,
+    GPIO0 = 0,
     GPIO1,
     GPIO2,
     GPIO3,
@@ -64,56 +64,56 @@ typedef enum {
     UART2_TX = GPIO8,
     UART2_RX = GPIO9,
 
-    I2C1_SCLK_1 	= GPIO2,
-    I2C1_SDATA_1 	= GPIO3,
-    I2C1_SCLK_2		= GPIO5,
-    I2C1_SDATA_2 	= GPIO4,
-    I2C1_SCLK 	= I2C1_SCLK_1,  /*Default*/
-    I2C1_SDATA 	= I2C1_SDATA_1,  /*Default*/
-
-    I2C2_SCLK_1 	= GPIO14,
-    I2C2_SDATA_1 	= GPIO15,
-    I2C2_SCLK_2 	= GPIO17,
-    I2C2_SDATA_2 	= GPIO16,
-    I2C2_SCLK 	= I2C2_SCLK_2,  /*Default*/
-    I2C2_SDATA 	= I2C2_SDATA_2,  /*Default*/
-    I2C_SCL 	= I2C1_SCLK_1,  /*Default*/
-    I2C_SDA 	= I2C1_SDATA_1,  /*Default*/
+    I2C1_SCLK_1    = GPIO2,
+    I2C1_SDATA_1   = GPIO3,
+    I2C1_SCLK_2    = GPIO5,
+    I2C1_SDATA_2   = GPIO4,
+    I2C1_SCLK      = I2C1_SCLK_1,   /*Default*/
+    I2C1_SDATA     = I2C1_SDATA_1,  /*Default*/
+
+    I2C2_SCLK_1    = GPIO14,
+    I2C2_SDATA_1   = GPIO15,
+    I2C2_SCLK_2    = GPIO17,
+    I2C2_SDATA_2   = GPIO16,
+    I2C2_SCLK      = I2C2_SCLK_2,  /*Default*/
+    I2C2_SDATA     = I2C2_SDATA_2, /*Default*/
+    I2C_SCL        = I2C1_SCLK_1,  /*Default*/
+    I2C_SDA        = I2C1_SDATA_1, /*Default*/
 
     /* SPI 1 with 1st set of CROSS BAR */
-    SPI1_SSNO0_1	= GPIO0,
-    SPI1_SSNO1_1	= GPIO1,
-    SPI1_SSNO2_1	= GPIO2,
-    SPI1_SSNO3_1	= GPIO3,
+    SPI1_SSNO0_1    = GPIO0,
+    SPI1_SSNO1_1    = GPIO1,
+    SPI1_SSNO2_1    = GPIO2,
+    SPI1_SSNO3_1    = GPIO3,
 
     /* SPI 1 with 2st set of CROSS BAR */
-    SPI1_SCLK_2 	= GPIO4,
-    SPI1_SDATAO_2	= GPIO5,
-    SPI1_SDATAI_2 	= GPIO6,
-    SPI1_SSNI_2 	= GPIO7,
-    SPI1_SSNO0_2 	= GPIO8,
-    SPI1_SSNO1_2 	= GPIO9,
-    SPI1_SSNO2_2 	= GPIO10,
-
-    SPI1_SCLK 	= SPI1_SCLK_2,  /*Default*/
-    SPI1_SDATAO	= SPI1_SDATAO_2, /*Default*/
-    SPI1_SDATAI 	= SPI1_SDATAI_2,  /*Default*/
-    SPI1_SSNI 	= SPI1_SSNI_2,  /*Default*/
-    SPI1_SSNO0 	= SPI1_SSNO0_2,  /*Default*/
-    SPI1_SSNO1 	= SPI1_SSNO1_2,  /*Default*/
-    SPI1_SSNO2 	= SPI1_SSNO2_2,  /*Default*/
+    SPI1_SCLK_2      = GPIO4,
+    SPI1_SDATAO_2    = GPIO5,
+    SPI1_SDATAI_2    = GPIO6,
+    SPI1_SSNI_2      = GPIO7,
+    SPI1_SSNO0_2     = GPIO8,
+    SPI1_SSNO1_2     = GPIO9,
+    SPI1_SSNO2_2     = GPIO10,
+
+    SPI1_SCLK    = SPI1_SCLK_2,   /*Default*/
+    SPI1_SDATAO  = SPI1_SDATAO_2, /*Default*/
+    SPI1_SDATAI  = SPI1_SDATAI_2, /*Default*/
+    SPI1_SSNI    = SPI1_SSNI_2,   /*Default*/
+    SPI1_SSNO0   = SPI1_SSNO0_2,  /*Default*/
+    SPI1_SSNO1   = SPI1_SSNO1_2,  /*Default*/
+    SPI1_SSNO2   = SPI1_SSNO2_2,  /*Default*/
 
     /* SPI 1 with 3rd set of CROSS BAR */
-    SPI1_SCLK_3 	= GPIO8,
-    SPI1_SDATAO_3	= GPIO9,
-    SPI1_SDATAI_3 	= GPIO10,
+    SPI1_SCLK_3     = GPIO8,
+    SPI1_SDATAO_3   = GPIO9,
+    SPI1_SDATAI_3   = GPIO10,
 
     /* SPI 2 */
-    SPI2_SCLK 	= GPIO14,
-    SPI2_SDATAO = GPIO15,
-    SPI2_SDATAI = GPIO16,
-    SPI2_SSNI 	= GPIO17,
-    SPI2_SSNO0 	= GPIO17,
+    SPI2_SCLK     = GPIO14,
+    SPI2_SDATAO   = GPIO15,
+    SPI2_SDATAI   = GPIO16,
+    SPI2_SSNI     = GPIO17,
+    SPI2_SSNO0    = GPIO17,
 
     // Generic signals namings
     LED1        = GPIO4,
@@ -157,17 +157,17 @@ typedef enum {
 } PinDirection;
 
 typedef enum {
-    PushPullPullDown = 0,
-    PushPullNoPull = 1,
-    PushPullPullUp = 2,
+    PushPullPullDown  = 0,
+    PushPullNoPull    = 1,
+    PushPullPullUp    = 2,
     OpenDrainPullDown = 3,
-    OpenDrainNoPull = 4,
-    OpenDrainPullUp = 5,
-    PullNone  = PushPullNoPull,
-    PullUp    = PushPullPullUp,
-    PullDown  = PushPullPullDown,
-    OpenDrain = OpenDrainPullUp,
-    PullDefault = PullNone
+    OpenDrainNoPull   = 4,
+    OpenDrainPullUp   = 5,
+    PullNone          = PushPullNoPull,
+    PullUp            = PushPullPullUp,
+    PullDown          = PushPullPullDown,
+    OpenDrain         = OpenDrainPullUp,
+    PullDefault       = PullNone
 
 } PinMode;
 

targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar.h

@@ -43,16 +43,16 @@ extern "C" {
 #endif
 
 /* ADC register bits */
-#define ADC_CONTROL_MODE_BIT_POS		0
-#define ADC_CONTROL_MEASTYPE_BIT_POS	3
-#define ADC_CONTROL_INPUTSCALE_BIT_POS	4
-#define ADC_CONTROL_MEAS_CH_BIT_POS		8
-#define ADC_CONTROL_REF_CH_BIT_POS		12
-#define ADC_PRESCALE_VAL_BIT_POS		0
-#define ADC_PRESCALE_EN_BIT_POS			8
-#define ADC_DELAY_SAMPLE_RATE_BIT_POS	0
-#define ADC_DELAY_WARMUP_BIT_POS		16
-#define ADC_DELAY_SAMPLE_TIME_BIT_POS	24
+#define ADC_CONTROL_MODE_BIT_POS        0
+#define ADC_CONTROL_MEASTYPE_BIT_POS    3
+#define ADC_CONTROL_INPUTSCALE_BIT_POS  4
+#define ADC_CONTROL_MEAS_CH_BIT_POS     8
+#define ADC_CONTROL_REF_CH_BIT_POS      12
+#define ADC_PRESCALE_VAL_BIT_POS        0
+#define ADC_PRESCALE_EN_BIT_POS         8
+#define ADC_DELAY_SAMPLE_RATE_BIT_POS   0
+#define ADC_DELAY_WARMUP_BIT_POS        16
+#define ADC_DELAY_SAMPLE_TIME_BIT_POS   24
 
 typedef enum {
     ADC_CHANNEL0 = 0,

targets/TARGET_ONSEMI/TARGET_NCS36510/adc_sar_map.h

@@ -45,13 +45,13 @@ typedef struct {
         struct {
             __IO uint32_t MODE :1;             /** 1= Continuous Conversion 0= Single Shot  */
             __IO uint32_t START_CONV :1;       /** 1= Start Conversion 0= No effect*/
-            __IO uint32_t ABORT :1;			   /** 1= Aborts the Continuous Conversion mode 0=No effect */
+            __IO uint32_t ABORT :1;            /** 1= Aborts the Continuous Conversion mode 0=No effect */
             __IO uint32_t MEASUREMENT_TYPE :1; /** 1= Absolute 0= Differential */
             __IO uint32_t INPUT_SCALE :3;      /** 000 – 1.0     001 – 0.6923 010 – 0.5294 011 – 0.4286 100 – 0.3600 101 – 0.3103  110 – 0.2728 111 – 0.2432 */
-            __I  uint32_t BIT7:1;			   /** NA Always read backs 0*/
-            __IO uint32_t CONV_CH :3;		   /** Selects 1 or 8 channels to do a conversion on. 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor      111 – Battery  */
-            __I uint32_t  NA :1;			   /** NA */
-            __IO uint32_t REF_CH :3;		   /** Selects 1 to 8 channels for reference channel  000 – A[0]  000 – A[1]   010 – A[2]  011 – A[3]  100 – N/A  101 – N/A 110 – Temperature sensor  111 – Battery */
+            __I  uint32_t BIT7:1;              /** NA Always read backs 0*/
+            __IO uint32_t CONV_CH :3;          /** Selects 1 or 8 channels to do a conversion on. 000 – A[0] 000 – A[1] 010 – A[2] 011 – A[3] 100 – N/A 101 – N/A 110 – Temperature sensor      111 – Battery  */
+            __I uint32_t  NA :1;               /** NA */
+            __IO uint32_t REF_CH :3;           /** Selects 1 to 8 channels for reference channel  000 – A[0]  000 – A[1]   010 – A[2]  011 – A[3]  100 – N/A  101 – N/A 110 – Temperature sensor  111 – Battery */
         } BITS;
         __IO uint32_t WORD;
     } CONTROL;
@@ -67,9 +67,9 @@ typedef struct {
     __IO uint32_t IR;
     union {
         struct {
-            __IO uint32_t PRESC_VAL  :8; /**Set the pre-scalar value. The SAR ADC nominally runs at 4MHz, so this value should be programmed to 32 Mhz/4mhz -1=7 */
-            __IO uint32_t PRESC_EN   :1; /** 1= enables PreScalar 0= Disable Prescalar */
-//			__IO uint32_t PHASE_CTRL :1; /** 1 = Phase 2 is delayed two 32MHz clock from phase 1. 0= Phase 2 is delayed one 32MHz clock from phase 1. */
+            __IO uint32_t PRESC_VAL  :8;   /**Set the pre-scalar value. The SAR ADC nominally runs at 4MHz, so this value should be programmed to 32 Mhz/4mhz -1=7 */
+            __IO uint32_t PRESC_EN   :1;   /** 1= enables PreScalar 0= Disable Prescalar */
+//            __IO uint32_t PHASE_CTRL :1; /** 1 = Phase 2 is delayed two 32MHz clock from phase 1. 0= Phase 2 is delayed one 32MHz clock from phase 1. */
         } BITS;
         __IO uint32_t WORD;
     } PRESCALE;

targets/TARGET_ONSEMI/TARGET_NCS36510/architecture.h

@@ -53,24 +53,24 @@
 *************************************************************************************************/
 
 /* Interrupt Control and State Register (0xE000ED04)
- * 31 		NMIPENDSET 			R/W 	0 		NMI pended
- * 28 		PENDSVSET 			R/W 	0 		Write 1 to pend system call; Read value
- * 												indicates pending status
- * 27 		PENDSVCLR 			W 		0 		Write 1 to clear PendSV pending status
- * 26 		PENDSTSET 			R/W 	0 		Write 1 to pend Systick exception; Read
- *												value indicates pending status
- * 25 		PENDSTCLR 			W 		0 		Write 1 to clear Systick pending status
- * 23 		ISRPREEMPT 			R 		0 		Indicate that a pending interrupt is going
- *												to be active in next step (for debug)
- * 22 		ISRPENDING 			R 		0 		External interrupt pending (excluding
- *												system exceptions such as NMI for
- *												fault)
- * 21:12 	VECTPENDING 		R 		0 		Pending ISR number
- * 11 		RETTOBASE 			R 		0 		Set to 1 when the processor is running
- * 												an exception handler and will return to
- *												thread level if interrupt return and no
- *												other exceptions pending
- * 9:0 		VECTACTIVE 			R 		0 		Current running interrupt service routine
+ * 31         NMIPENDSET            R/W     0     NMI pended
+ * 28         PENDSVSET             R/W     0     Write 1 to pend system call; Read value
+ *                                                indicates pending status
+ * 27         PENDSVCLR             W       0     Write 1 to clear PendSV pending status
+ * 26         PENDSTSET             R/W     0     Write 1 to pend Systick exception; Read
+ *                                                value indicates pending status
+ * 25         PENDSTCLR             W       0     Write 1 to clear Systick pending status
+ * 23         ISRPREEMPT            R       0     Indicate that a pending interrupt is going
+ *                                                to be active in next step (for debug)
+ * 22         ISRPENDING            R       0     External interrupt pending (excluding
+ *                                                system exceptions such as NMI for
+ *                                                fault)
+ * 21:12     VECTPENDING            R       0     Pending ISR number
+ * 11         RETTOBASE             R       0     Set to 1 when the processor is running
+ *                                                an exception handler and will return to
+ *                                                thread level if interrupt return and no
+ *                                                other exceptions pending
+ * 9:0         VECTACTIVE           R       0     Current running interrupt service routine
  */
 #define RUNNING_IN_ISR  (((SCB->ICSR & 0x3FF) > 0 ) ? 1 : 0)
 

targets/TARGET_ONSEMI/TARGET_NCS36510/assert_onsemi.h

@@ -55,15 +55,15 @@ void fOnAssert(const char *filename, unsigned int line);
 /** Can be assigned to hook into the assertion. */
 extern void (*assertCallback)(const char *filename, unsigned int line);
 
-#define ASSERT(test)		((test) ? (void)0 : fOnAssert(__FILE__, __LINE__))
+#define ASSERT(test)        ((test) ? (void)0 : fOnAssert(__FILE__, __LINE__))
 
-#define VERIFY(test)		ASSERT(test)
+#define VERIFY(test)        ASSERT(test)
 
 #else
 
-#define ASSERT(test)		((test) ? (void)0 : 1)
+#define ASSERT(test)        ((test) ? (void)0 : 1)
 
-#define VERIFY(test)		((void)(test))
+#define VERIFY(test)        ((void)(test))
 
 #endif // DEBUG
 

targets/TARGET_ONSEMI/TARGET_NCS36510/char_driver.h

@@ -42,8 +42,8 @@
 
 #include "driver.h"
 
-#define DRV_NO_ERROR			(True)
-#define DRV_ERROR				(False)
+#define DRV_NO_ERROR       (True)
+#define DRV_ERROR          (False)
 
 /** A character driver structure. */
 typedef struct char_driver {