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[RISCV] Add Andes XAndesperf (Andes Performance) extension. (llvm#135110)
The spec can be found at: https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release. This patch only supports assembler. Relocation and fixup for the branch and gp-implied instructions will be added in a later patch.
1 parent 011e514 commit 55dbed1

18 files changed

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-21
lines changed

‎clang/test/Driver/print-supported-extensions-riscv.c

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@@ -156,6 +156,7 @@
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// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity)
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// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
158158
// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
159+
// CHECK-NEXT: xandesperf 5.0 'XAndesPerf' (Andes Performance Extension)
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// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations)
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// CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching)
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// CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation)

‎llvm/docs/RISCVUsage.rst

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@@ -505,6 +505,9 @@ The current vendor extensions supported are:
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``experimental-XRivosVizip``
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LLVM implements `version 0.1 of the Rivos Vector Register Zips extension specification <https://github.com/rivosinc/rivos-custom-extensions>`__.
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508+
``XAndesPerf``
509+
LLVM implements `version 5.0.0 of the Andes Performance Extension specification <https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf>` by Andes Technology. All instructions are prefixed with `nds.` as described in the specification.
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508511
Experimental C Intrinsics
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=========================
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‎llvm/docs/ReleaseNotes.md

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@@ -175,6 +175,7 @@ Changes to the RISC-V Backend
175175
`Zsfmclic` for the M-mode registers and `Zsfsclic` for the S-mode registers.
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* Adds Support for SiFive CLIC interrupt attributes, which automate writing CLIC
177177
interrupt handlers without using inline assembly.
178+
* Adds assembler support for the Andes `XAndesperf` (Andes Performance extension).
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179180
Changes to the WebAssembly Backend
180181
----------------------------------

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

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Original file line numberDiff line numberDiff line change
@@ -852,6 +852,10 @@ struct RISCVOperand final : public MCParsedAsmOperand {
852852
return SignExtend64<32>(Imm);
853853
}
854854

855+
bool isSImm11Lsb0() const {
856+
return isSImmPred([](int64_t Imm) { return isShiftedInt<10, 1>(Imm); });
857+
}
858+
855859
bool isSImm12() const {
856860
if (!isImm())
857861
return false;
@@ -944,6 +948,22 @@ struct RISCVOperand final : public MCParsedAsmOperand {
944948
[](int64_t Imm) { return Imm != INT64_MIN && isInt<5>(Imm - 1); });
945949
}
946950

951+
bool isSImm18() const {
952+
return isSImmPred([](int64_t Imm) { return isInt<18>(Imm); });
953+
}
954+
955+
bool isSImm18Lsb0() const {
956+
return isSImmPred([](int64_t Imm) { return isShiftedInt<17, 1>(Imm); });
957+
}
958+
959+
bool isSImm19Lsb00() const {
960+
return isSImmPred([](int64_t Imm) { return isShiftedInt<17, 2>(Imm); });
961+
}
962+
963+
bool isSImm20Lsb000() const {
964+
return isSImmPred([](int64_t Imm) { return isShiftedInt<17, 3>(Imm); });
965+
}
966+
947967
bool isSImm32Lsb0() const {
948968
return isSImmPred([](int64_t Imm) { return isShiftedInt<31, 1>(Imm); });
949969
}
@@ -1515,6 +1535,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
15151535
case Match_InvalidSImm11:
15161536
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 10),
15171537
(1 << 10) - 1);
1538+
case Match_InvalidSImm11Lsb0:
1539+
return generateImmOutOfRangeError(
1540+
Operands, ErrorInfo, -(1 << 10), (1 << 10) - 2,
1541+
"immediate must be a multiple of 2 bytes in the range");
15181542
case Match_InvalidUImm10:
15191543
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 10) - 1);
15201544
case Match_InvalidUImm11:
@@ -1587,6 +1611,21 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
15871611
(1 << 4),
15881612
"immediate must be in the range");
15891613
}
1614+
case Match_InvalidSImm18:
1615+
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 17),
1616+
(1 << 17) - 1);
1617+
case Match_InvalidSImm18Lsb0:
1618+
return generateImmOutOfRangeError(
1619+
Operands, ErrorInfo, -(1 << 17), (1 << 17) - 2,
1620+
"immediate must be a multiple of 2 bytes in the range");
1621+
case Match_InvalidSImm19Lsb00:
1622+
return generateImmOutOfRangeError(
1623+
Operands, ErrorInfo, -(1 << 18), (1 << 18) - 4,
1624+
"immediate must be a multiple of 4 bytes in the range");
1625+
case Match_InvalidSImm20Lsb000:
1626+
return generateImmOutOfRangeError(
1627+
Operands, ErrorInfo, -(1 << 19), (1 << 19) - 8,
1628+
"immediate must be a multiple of 8 bytes in the range");
15901629
case Match_InvalidSImm26:
15911630
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
15921631
(1 << 25) - 1);

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 9 additions & 6 deletions
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@@ -447,15 +447,15 @@ static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
447447
return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
448448
}
449449

450-
template <unsigned N>
451-
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint32_t Imm,
450+
template <unsigned T, unsigned N>
451+
static DecodeStatus decodeSImmOperandAndLslN(MCInst &Inst, uint32_t Imm,
452452
int64_t Address,
453453
const MCDisassembler *Decoder) {
454-
assert(isUInt<N>(Imm) && "Invalid immediate");
455-
// Sign-extend the number in the bottom N bits of Imm after accounting for
456-
// the fact that the N bit immediate is stored in N-1 bits (the LSB is
454+
assert(isUInt<T - N + 1>(Imm) && "Invalid immediate");
455+
// Sign-extend the number in the bottom T bits of Imm after accounting for
456+
// the fact that the T bit immediate is stored in T-N bits (the LSB is
457457
// always zero)
458-
Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
458+
Inst.addOperand(MCOperand::createImm(SignExtend64<T>(Imm << N)));
459459
return MCDisassembler::Success;
460460
}
461461

@@ -727,6 +727,8 @@ static constexpr FeatureBitset XTHeadGroup = {
727727
RISCV::FeatureVendorXTHeadMemPair, RISCV::FeatureVendorXTHeadSync,
728728
RISCV::FeatureVendorXTHeadVdot};
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730+
static constexpr FeatureBitset XAndesGroup = {RISCV::FeatureVendorXAndesPerf};
731+
730732
static constexpr DecoderListEntry DecoderList32[]{
731733
// Vendor Extensions
732734
{DecoderTableXVentana32,
@@ -740,6 +742,7 @@ static constexpr DecoderListEntry DecoderList32[]{
740742
{DecoderTableXmipscmov32,
741743
{RISCV::FeatureVendorXMIPSCMov},
742744
"MIPS mips.ccmov"},
745+
{DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
743746
// Standard Extensions
744747
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
745748
{DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

Lines changed: 7 additions & 5 deletions
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@@ -92,7 +92,8 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
9292
SmallVectorImpl<MCFixup> &Fixups,
9393
const MCSubtargetInfo &STI) const;
9494

95-
uint64_t getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
95+
template <unsigned N>
96+
unsigned getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
9697
SmallVectorImpl<MCFixup> &Fixups,
9798
const MCSubtargetInfo &STI) const;
9899

@@ -535,16 +536,17 @@ RISCVMCCodeEmitter::getImmOpValueSlist(const MCInst &MI, unsigned OpNo,
535536
}
536537
}
537538

538-
uint64_t
539-
RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
539+
template <unsigned N>
540+
unsigned
541+
RISCVMCCodeEmitter::getImmOpValueAsrN(const MCInst &MI, unsigned OpNo,
540542
SmallVectorImpl<MCFixup> &Fixups,
541543
const MCSubtargetInfo &STI) const {
542544
const MCOperand &MO = MI.getOperand(OpNo);
543545

544546
if (MO.isImm()) {
545547
uint64_t Res = MO.getImm();
546-
assert((Res & 1) == 0 && "LSB is non-zero");
547-
return Res >> 1;
548+
assert((Res & ((1 << N) - 1)) == 0 && "LSB is non-zero");
549+
return Res >> N;
548550
}
549551

550552
return getImmOpValue(MI, OpNo, Fixups, STI);

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -1508,6 +1508,15 @@ def HasVendorXRivosVizip
15081508
AssemblerPredicate<(all_of FeatureVendorXRivosVizip),
15091509
"'XRivosVizip' (Rivos Vector Register Zips)">;
15101510

1511+
// Andes Extension(s)
1512+
1513+
def FeatureVendorXAndesPerf
1514+
: RISCVExtension<5, 0, "Andes Performance Extension">;
1515+
def HasVendorXAndesPerf
1516+
: Predicate<"Subtarget->hasVendorXAndesPerf()">,
1517+
AssemblerPredicate<(all_of FeatureVendorXAndesPerf),
1518+
"'XAndesPerf' (Andes Performance Extension)">;
1519+
15111520
//===----------------------------------------------------------------------===//
15121521
// LLVM specific features and extensions
15131522
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

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@@ -279,8 +279,8 @@ def simm12_no6 : ImmLeaf<XLenVT, [{
279279
def bare_simm13_lsb0 : Operand<OtherVT> {
280280
let ParserMatchClass = BareSImmNLsb0AsmOperand<13>;
281281
let PrintMethod = "printBranchOperand";
282-
let EncoderMethod = "getImmOpValueAsr1";
283-
let DecoderMethod = "decodeSImmOperandAndLsl1<13>";
282+
let EncoderMethod = "getImmOpValueAsrN<1>";
283+
let DecoderMethod = "decodeSImmOperandAndLslN<13, 1>";
284284
let MCOperandPredicate = [{
285285
int64_t Imm;
286286
if (MCOp.evaluateAsConstantImm(Imm))
@@ -316,8 +316,8 @@ def Simm21Lsb0JALAsmOperand : BareSImmNLsb0AsmOperand<21> {
316316
def simm21_lsb0_jal : Operand<OtherVT> {
317317
let ParserMatchClass = Simm21Lsb0JALAsmOperand;
318318
let PrintMethod = "printBranchOperand";
319-
let EncoderMethod = "getImmOpValueAsr1";
320-
let DecoderMethod = "decodeSImmOperandAndLsl1<21>";
319+
let EncoderMethod = "getImmOpValueAsrN<1>";
320+
let DecoderMethod = "decodeSImmOperandAndLslN<21, 1>";
321321
let MCOperandPredicate = [{
322322
int64_t Imm;
323323
if (MCOp.evaluateAsConstantImm(Imm))
@@ -2189,6 +2189,7 @@ include "RISCVInstrInfoXqci.td"
21892189
include "RISCVInstrInfoXqccmp.td"
21902190
include "RISCVInstrInfoXMips.td"
21912191
include "RISCVInstrInfoXRivos.td"
2192+
include "RISCVInstrInfoXAndes.td"
21922193

21932194
//===----------------------------------------------------------------------===//
21942195
// Global ISel

‎llvm/lib/Target/RISCV/RISCVInstrInfoC.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -142,8 +142,8 @@ def bare_simm9_lsb0 : Operand<OtherVT>,
142142
ImmLeaf<XLenVT, [{return isShiftedInt<8, 1>(Imm);}]> {
143143
let ParserMatchClass = BareSImmNLsb0AsmOperand<9>;
144144
let PrintMethod = "printBranchOperand";
145-
let EncoderMethod = "getImmOpValueAsr1";
146-
let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
145+
let EncoderMethod = "getImmOpValueAsrN<1>";
146+
let DecoderMethod = "decodeSImmOperandAndLslN<9, 1>";
147147
let MCOperandPredicate = [{
148148
int64_t Imm;
149149
if (MCOp.evaluateAsConstantImm(Imm))
@@ -206,8 +206,8 @@ def bare_simm12_lsb0 : Operand<OtherVT>,
206206
ImmLeaf<XLenVT, [{return isShiftedInt<11, 1>(Imm);}]> {
207207
let ParserMatchClass = BareSImmNLsb0AsmOperand<12>;
208208
let PrintMethod = "printBranchOperand";
209-
let EncoderMethod = "getImmOpValueAsr1";
210-
let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
209+
let EncoderMethod = "getImmOpValueAsrN<1>";
210+
let DecoderMethod = "decodeSImmOperandAndLslN<12, 1>";
211211
let MCOperandPredicate = [{
212212
int64_t Imm;
213213
if (MCOp.evaluateAsConstantImm(Imm))

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